The electromigration (EM) immortality, exhibiting no sign of failure even after a prolonged duration of stress, can be attributed to the continuous supply of Cu from a wide underlying feeder through the via with poor barrier coverage. This type of barrier defect can artificially inflate the estimated EM lifetime, leading to a misleadingly optimistic reliability risk assessment in the lab. EM risk can also emerge in actual products due to the stringent design and aggressive scaling in advanced interconnects, especially with short-length EM rules. For EM risk mitigation, it is essential to have effective methods to reveal such barrier defects. This paper presents two PFA techniques for barrier integrity evaluation. The chemical etch method is very simple yet effective, and can be readily performed in general PFA labs. The STEM tomography requires an advanced TEM but can pinpoint the defect location.

AC TDDB (Time-Dependent-Dielectric-Breakdown) lifetime exhibits inconsistency at low frequencies (<10kHz), while it is reported to be longer at higher frequencies. In this study, AC TDDB mechanism is systematically investigated over a frequency range of 2Hz to 500kHz. Notably, n-type transistors with bi-layer gate stack demonstrate degradation of AC TDDB lifetime below that of DC TDDB in both FinFET and Planar devices. This degradation worsens as the gate oxide thickness decreases, a phenomenon explained by Maxwell-Wagner instability. To mitigate this degradation at low frequencies (LF), applying a small positive voltage during the off-state of the AC pulse (Vr) can improve reliability, particularly in circuits operating at low frequencies.

We performed a systematic study on hot carrier injection (HCI) in I/O FinFETs using various source/drain (S/D) extension implantation and geometry modulation schemes. While previous publications focused on nMOS, we extended our investigation to pMOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. Electrical characterization and 3D TCAD simulation confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. In this paper, we summarized various strategies that can be used to optimize the process for both HCI reliability and performance of nMOS and pMOS FinFETs.

Impacts of BEOL queue time (Q-Time) from post-Cu CMP (Chemical Mechanical Polish) to SiCN capping layer on reliability were investigated. Degradation in electromigration (EM) was observed in both Cu/Low-k (LK) and Cu/Ultra-low-k (ULK) interconnects due to Cu surface oxidation. However, there is no reliability impact in LK dielectric, while significant degradation in ULK dielectric. EM degradation in long CMP Q-Time could be recovered by CMP Buff process.

We performed a systematic study on hot carrier injection (HCI) in I/O FinFETs using various source/drain (S/D) extension implantation and geometry modulation schemes. While previous publications focused on nMOS, we extended our investigation to pMOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. Electrical characterization and 3D TCAD simulation confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. In this paper, we summarized various strategies that can be used to optimize the process for both HCI reliability and performance of nMOS and pMOS FinFETs.

Stress polarity dependency of MOL-TDDB (Middle of Line-Time Dependent Dielectric Breakdown) is investigated on FinFET devices. Due to asymmetry in spacer dielectrics between Gate (PC) and Contact (CA), MOL-TDDB reliability can be different by bias polarity. From Vramp and TDDB evaluations, we observed MOL-TDDB reliability becomes worse when positive bias is applied to the CA side. Leakage current analysis and energy band diagram study suggested this reliability degradation can be explained by either more trap generation or more electron trapping in high-k layer (on PC side). This behavior can be suppressed by Vt-tuning capping layer.

To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ( $\tau_{\mathrm{c}}/\tau_{\mathrm{e}}$ , or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $\mathbf{RTN}\downarrow$ , bias temperature instability (BTI) $\mathbf{recovery}\uparrow$ , SRAM SNM $\mathbf{shift}\downarrow$ ) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.

The effect of reverse body bias on hot carrier (HCI) reliability is studied in details at CHE (channel hot carrier) and DAHC (drain avalanche hot carrier) stress conditions in advanced standard gate n-channel FinFET transistors. HCI degradation is found to be independent of reverse body bias, when the body bias, Vb is low (0V ~ -1V). However, HCI starts to aggravate at further negative Vb (-1V ~ -2V) for both CHE and DAHC conditions, showing strong dependence on the transverse electric field. The physical mechanism is attributed to the increased e-h pair generations, enhancing electron trapping in the gate oxide. This study addresses a key reliability constraint for circuit designers while designing tuned body bias circuitry.

For high voltage application at a fixed inter-metal distance, dielectric reliability has been investigated on multi-layer inter-level interconnects, focusing on conduction mechanism and geometry effect. From Vramp (voltage-ramp-to-breakdown) tests, Vbd is found to be 4-5% lower with positive bias applied to the bottom metal, which is believed to be due to the polarity-dependent conduction mechanism. IV characteristics of two different bias configurations at various temperatures suggest that Poole-Frenkel and Fowler-Nordheim, respectively, dominates for a high bias to the bottom and top electrodes. In addition, metal density affects the lifetime of inter-level TDDB (time dependent dielectric breakdown) with Poisson area scaling. Based on our studies, a guideline for additional reliability margin can be proposed by bias polarity restriction and layout design optimization.

Reliability of Core and IO FinFET is extensively investigated with various process steps at Fin, Source/ Drain, sacrificial Gate-Metal, and High-Pressure D2 Anneal. By modulating the process knobs, we quantified the effect of oxide traps (at bulk or interface) on reliability mechanisms of replacement metal gate (RMG). The results are summarized as a process-reliability optimization guideline.

Basic Reliability of IO FinFET is studied with various process options and extensive trap density investigation. It is observed that the NBTI margin on High Performance IO pFET is lowered by additional treatment to maintain the taller Fin profile. Trap density investigation with charge pumping identified the source of oxide traps in tall FinFET and the mechanism of NBTI degradation. Finally, after oxide trap reduction, FinFET process was improved for both reliability and performance.

CMOS Image Sensor(CIS) products need higher voltage device and better analog characteristics than conventional SOC & Logic products. This work presents newly developed 14nm FinFET process with 2.xV high voltage FinFET device characteristics showing excellent analog and low power digital characteristics comparing to 28nm planar process. Gm is improved by 30% and 67% in FinFET process for NMOS and PMOS, respectively. Rout characteristics increased by 40 times and 6 times over 28nm planar process. Interface state density(Nit) improved by more than 40% and flicker noise characteristics also improved by 64% and 42% for NMOS and PMOS, respectively. Digital logic Transistor ion-ioff performance improved by by 32% and by 211% for NMOS and PMOS, respectively compared to 28nm planar device and the chip power consumption of digital logic functional block reduced by 34% in real Si of 12M pixel product. 14nm FinFET process expected to improve power consumption by 42% in 144M pixel density.

The effect of Joule heating (JH) on electromigration (EM) was investigated using copper low-k interconnects. We found Black's empirical EM model works at a very wide stress conditions (I = 0.03 mA ∼ 3.5mA), where the temperature rise by JH ranges from 0°C to 240°C. EM modeling parameters were found to be 1.05eV and 1.4 for EM Ea and n, respectively. Extensive failure analysis and FEM simulations were carried out to understand the EM failure mode at various JH conditions and provide guidelines for the usage of JH-assisted EM test method and design-reliability rules.

Moisture impact on dielectric reliability was investigated with intentional moisture uptake and removal from porous low-k dielectric. In our tests, moisture can reduce TDDB lifetimes by 6 orders, while the kinetics is maintained (for both dry and wet samples). Interestingly, moisture from humid atmosphere does not increase the leakage current, but can reduce TDDB lifetimes significantly. So, the leakage current is not a good index to detect moisture-induced TDDB degradation. TDDB tests with various pre-bake conditions show moisture removal is not linear over bake temperatures, indicating multiple moisture states in low-k dielectric. Moisture diffusion, scaled from our test condition, shows moisture can diffuse few micro-meters in one second into low-k dielectric even at room temperature and impact dielectric reliability. To recover from the moisture damage, we recommend a high bake temperature (300°C∼350°C).

The film cooling performance of cylindrical holes embedded in a transverse trench is evaluated for various shapes of the trench and blowing ratios, and an optimum geometry for the trenched film-cooling hole is suggested. In order to analyze the turbulent flow and film cooling performance, three-dimensional Reynolds-averaged Navier-Stokes analysis is performed using the shear stress transport turbulence model. Tetrahedral and hexahedral computational meshes are tested, and the numerical solution is validated by comparison with experimental data. A parametric study with two geometric variables, the height and width of the trench, is performed. From the results of the parametric study and flow field analysis, shifting the film cooling hole toward the upstream end of the trench is proposed to enhance film cooling performance. In addition, the optimum downstream trench width is determined.

Multi-objective shape optimization of a row of laidback fan-shaped film cooling holes has been performed using a hybrid multi-objective evolutionary approach in order to achieve an acceptable compromise between two competing objectives: the enhancement of film cooling effectiveness and the reduction of aerodynamic loss. In order to perform comprehensive optimization of a film cooling hole shape, the injection angle of the hole, lateral expansion angle of the diffuser, forward expansion angle of the hole, and pitch-to-hole diameter ratio are chosen as design variables. Forty experimental designs within the design spaces are selected using the Latin hypercube sampling method. The response surface approximation method is used to construct the surrogate using objective function values calculated at the experimental points using Reynolds-averaged Navier-Stokes analysis. The shear stress transport turbulence model is used as a turbulence closure. The optimization results are processed using the Pareto-optimal method. The Pareto-optimal solutions are obtained using a combination of a evolutionary algorithm and a local search method. The optimum designs are grouped using the k-means clustering technique, and the three optimal points selected in the Pareto-optimal solutions are evaluated by numerical analysis. The optimum designs give enhanced objective function values compared to the experimental designs.

A parametric analysis and optimization of double-jet film-cooling holes was performed using three-dimensional Reynolds averaged Navier-Stokes equations with the shear stress transport turbulence model. The numerical results for film-cooling effectiveness were validated in comparison with experimental data. The lateral and streamwise distances between the centers of the holes, along with two lateral ejection angles, were chosen as the design variables. The effects of these four variables on the film-cooling effectiveness were evaluated. For optimization of double-jet film-cooling holes, film-cooling effectiveness was considered as the objective function. Latin hypercube sampling was used to determine the design points. A weighted average surrogate model was constructed using the objective function values calculated at the design points. Sequential quadratic programming was used to search for the optimal point from the constructed surrogate. The cooling performance of double-jet film-cooling holes was improved considerably by optimization in comparison with the reference geometry.

VIATOP (VT), Aluminum Via connecting the bond pad and the Top Copper level, is the critical component for Bond Pad (BP) Electromigration (EM) in advanced technology nodes, where a smaller VT or its array is employed for maximum chip-scaling. In this study, we evaluated BP EM using various dimensions of VT, investigated the scaling effect, and proposed a BP EM model for current crowding & reservoir effect in the VT.

The effects of the ejection and lateral ejection angles of double-jet film-cooling holes on the film-cooling effectiveness was evaluated, and the shape of the double-jet film-cooling holes was optimized using three-dimensional Reynolds-averaged Navier–Stokes equations with a shear stress transport turbulence model and a radial basis neural network surrogate model. The numerical results for the film-cooling effectiveness were validated by a comparison with experimental data. To optimize the double jet film-cooling holes, the spatially-averaged, film-cooling effectiveness was considered as the objective function. Latin hypercube sampling was performed to determine the design points in the design space. A radial basis neural network model was constructed using the objective function values calculated at the design points. The optimal point was obtained from the constructed surrogate using sequential quadratic programming. The cooling performance of the double-jet film-cooling holes was improved considerably by optimization compared to the reference geometry. The constructed surrogate model was found to be sufficiently reliable.