We performed a systematic study on hot carrier injection (HCI) in I/O FinFETs using various source/drain (S/D) extension implantation and geometry modulation schemes. While previous publications focused on nMOS, we extended our investigation to pMOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. Electrical characterization and 3D TCAD simulation confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. In this paper, we summarized various strategies that can be used to optimize the process for both HCI reliability and performance of nMOS and pMOS FinFETs.

We performed a systematic study on hot carrier injection (HCI) in I/O FinFETs using various source/drain (S/D) extension implantation and geometry modulation schemes. While previous publications focused on nMOS, we extended our investigation to pMOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. Electrical characterization and 3D TCAD simulation confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. In this paper, we summarized various strategies that can be used to optimize the process for both HCI reliability and performance of nMOS and pMOS FinFETs.

The electrostatic discharge (ESD) phenomenon is a critical reliability concern, and the charged device model (CDM) is well known for its relatively high voltage peak with few nanoseconds duration on the gate oxide (GOX), resulting in breakdown. However, as ESD design window shrinks, even GOX degradation before hard breakdown during component-level CDM qualification can cause reliability issues such as soft-failures. This degradation can be attributed to the quickly increased electric field on the GOX, leading to the rapid creation of trapped charges before catastrophic damage. This study analyzes CDM-induced bias temperature instability (BTI)-like degradation and models threshold voltage (Vth) shift using a very-fast transmission line pulse (VF-TLP) with 1ns pulse width and 200ps rise and fall time, generally proposed for CDM evaluation. The experiment was conducted with various VF-TLP voltage peaks, numbers of pulsing iterations and GOX areas. And, finally, Vth shift model considering statistical variation is presented. This model can be a guideline to prevent CDM-induced GOX degradation at an early design stage.

In this paper, we report the hot-carrier-degradation characterization of 3nm gate-alI-around (GAA) logic technology featuring multi-bridge-channel field-effect-transistor (FET) for accurate end-of-life (EOL) prediction. The commonly used power-law model is compared to the saturation model in wafer level reliability (WLR). For testing devices over EOL, a long-term hot-carrier-injection (HCI) test is conducted by using package methodology. The EOL HCI Si degradation value is revealed to be less than half of the calculated value by the power-law model. The saturation model, predicted from WLR, fits to the long-term HCI test result. EOL Vmax and %Id show that the saturation model is more accurate for predicting HCI EOL. AC HCI is conducted to verify width and delay time effects on Id degradation. Id degradation from AC HCI shows that the total width time affects HCI degradation more compared to frequency.

Stress polarity dependency of MOL-TDDB (Middle of Line-Time Dependent Dielectric Breakdown) is investigated on FinFET devices. Due to asymmetry in spacer dielectrics between Gate (PC) and Contact (CA), MOL-TDDB reliability can be different by bias polarity. From Vramp and TDDB evaluations, we observed MOL-TDDB reliability becomes worse when positive bias is applied to the CA side. Leakage current analysis and energy band diagram study suggested this reliability degradation can be explained by either more trap generation or more electron trapping in high-k layer (on PC side). This behavior can be suppressed by Vt-tuning capping layer.

To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ( $\tau_{\mathrm{c}}/\tau_{\mathrm{e}}$ , or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $\mathbf{RTN}\downarrow$ , bias temperature instability (BTI) $\mathbf{recovery}\uparrow$ , SRAM SNM $\mathbf{shift}\downarrow$ ) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.

In this paper, we report reliability assessment of the Multi-Bridge-Channel FET (MBCFET) adopted 3nm gate all around (GAA) logic technology in comparison with the 4 and 8nm FinFET logic technologies. A notable improvement on negative bias temperature instability (NBTI) of MBCFET is observed thanks to {100} dominance. Gate oxide time-dependent-dielectric-breakdown (TDDB) of the 3nm MBCFETs is comparable to that of the 4nm and 8nm FinFETs. Self-heat decoupled hot-carrier-injection (HCI) is similar to that of the 4nm FinFETs. Reduced conductance maximum (Gm,max) indicates that HCI degradation of the 3nm MBCFETs is dominated by interface damage mechanism. Middle-of-the-line (MOL) TDDB Weibull distribution shows that the 3nm MBCFETs have shorter time-to-failure (TTF) due to reduced lateral distance from gate to diffusion contact than other FinFET logic technologies. Due to an adoption of self-aligned-contact (SAC), the 3nm MBCFETs have similar behavior on MOL breakdown voltage (Vbd) at various diffusion contact misalignment to the 4nm FinFETs. The 3nm MBCFETs show antenna immunity up to 3x antenna ratio. Lastly, thermal cycle (TC) results indicate that the 3nm GAA logic technology has little lattice-related defects.

This paper proposes an accelerator-based neutron beam to evaluate thermal-neutron-induced soft-error rate (tnSER) in semiconductor devices. The thermal-neutron flux is sufficient for the tnSER evaluation in the beam, and the moderator for the beam is compact, and we can perform the tnSER test at many facilities. We have evaluated tnSER in an SRAM with the proposed beam and a nuclear reactor, and the tnSER is in good agreement between the tests with the proposed neutron beam and the nuclear reactor.

This paper presents thermal-neutron soft error rates (tnSER) in 7 nm bulk-FinFET technology with applied Cobalt (Co) contact. A thermal-neutron irradiation test at MURR shows tnSER reduction in the 7 nm: the tnSER in the 7 nm (Co-contact) is 0.0012X of the tnSER in 14 nm (Tungsten (W)-contact). Simulation analysis shows that tnSER changed by 0.21X due to the advancement of transistor technology (from 14nm to 7nm) and 0.0057X due to the change in contact-material (from W to Co).

Time dependent variability has become a significant concern for End-of-lifetime(EOL) reliability prediction for advanced technology with continuous scaling. In this work, we explore time dependent variability of BTI and HCI on our advanced FinFET technology to demonstrate that Defect-Centric model is a good candidate to describe both of them and there is no obvious difference between 8nm and 7nm for BTI and HCI variation η parameter. Thus, a framework is proposed for BTI and HCI EOL degradation prediction with given ppm criteria.

Self-heating effect (SHE, ∆Tsh) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced technology, which substantially impacts on the integrated circuit (IC)’s design schemes. In this work, a new heat-dissipation-path based SHE model is proposed to describe the heat spreading to layout proximity by interactive thermal resistance (Rth(i,j)). Meanwhile, Rth-matrix methodology is employed to account for SHE layout proximity effect by linear superposition algorithm. Therefore, ∆Tsh profile can be more accurately reckoned with account for thermal interaction effect.

In 10-nm node core FinFETs, we analyzed the cause of higher hot carrier degradation (HCD) in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain materials, which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle (MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the pure HCD mechanisms to occur more in pFinFETs, which has higher temperature than nFinFETs. However, in pFinFETs, unlike nFinFETs, interface traps can be generated due to negative-bias temperature instability (NBTI) that occurs by the reaction between inversion holes and electrons of Si-H bonds. Also, since NBTI deteriorates more as the temperature increases, the phenomenon of higher degradation in pFinFET than nFinFET can be explained with the NBTI mechanism. Therefore, we propose an additional NBTI mechanism that is caused by high device temperature in pFinFETs even in the HCD condition. In addition, the main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that NBTI is dominant in pFinFETs. Finally, NBTI that can occur in the HCD condition was predicted through technology computer-aided design (TCAD) simulation. As a result, degradation due to pure hot carriers without NBTI occurs more in nFinFETs than in pFinFETs.

During the past decades, FinFET has been the main device architecture to accelerate transistor performance. Since FinFET should be scaled down with multi-function replace metal gate (RMG) and narrow and taller fin shape, the reliability issues have been concerned as well. It is very important to address the current reliability consideration on evolutionary FinFET and would be helpful to consider the new device architecture like gate all around device beyond FinFET. The baseline reliability on gate dielectric TDDB and BTI is less impacted by work-function modulation for scaled FinFET. In order to meet the wide range of Vt, the additional dipole is utilized resulting in TDDB improvement. The self-heating effect (SHE) should be considered for the intrinsic reliability with very narrower vertical fin structure. The layout dependent self-heating characterization and its model are presented. The BEOL electro-migration needs to add the transistor level self-heating in the thermal aware EM model. Since MOL and BEOL pitch is aggressive reduced, the intrinsic reliability and extrinsic reliability should be considered at the same time. For the high-volume products, the extrinsic failures should be suppressed below ppm level. Since the physical spacing all across the critical is very close to direct tunneling regime, the TTF based reliability model should be considered with power law for FEOL, MOL and BEOL for FinFET technology and beyond.

In this letter, we investigate the threshold voltage shift (Delta V-th) by negative bias temperature instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk p -FinFET. To analyze the effect of NBTI in the presence of the SHE, the DC stress was performed under high-bias conditions, i.e., gate bias V-GS=-1.3 V and drain bias V-DS up to -1.3 V at room temperature, which was usually referred to as hot-carrier degradation (HCD) stress. It has been observed that the long-time (10 s similar to 10(3) s) power-law time exponent (n) decreases as V-DS increases, and n was very close to that of NBTI-induced Delta V-th rather than HCD-induced Delta V-th at V-GS=V-DS=-1.3 V. For the first time, computer-aided design simulations were performed in combination with SHE and NBTI. The effect of NBTI in p-FinFET is confirmed to contribute significantly to Delta V-th under DC HCD stress because of SHE. The influence of SHE is mitigated in high-frequency circuit operation, but special attention should be paid to NBTI issues due to the potential occurrence of SHE as the technology nodes shrink.

We examined how to verify the circuit aging performance regarding the easily missed, but considerable stress conditions of transistors. First, power-down mode of integrated circuits may influence unintended device degradation and cause aging-induced mismatching of the circuit. Next, Positive Bias Temperature Instability (PBTI) for PMOS, unlike NMOS, is less significant for device-level reliability, yet some PBTI degradation for PMOS may still cause risk in sensitive circuit. These aging verification methods developed here can help circuit designers against aging and provide more robust product solutions.

In this article, we report the reliability characterization of 7-nm technology, in which the highly scaled sixth generation of FinFETs and 256-Mb static random access memory (SRAM) cells were newly developed by featuring extreme ultraviolet (EUV). The intrinsic reliability mechanisms of 7-nm FinFET including hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric-breakdown (TDDB) are similar to that of the previous nodes, and would not be degraded by introducing the scaled FinFET. Moreover, we found that the use of EUV single patterning of middle of line (MOL) and back end of line (BEOL) improves reliability distribution remarkably as compared to the previous nodes using argon fluoride (ArF) multiple patterning techniques. We successfully demonstrated SRAM and logic high-temperature operating life (HTOL) up to 500 h, indicating the robustness of product-level reliability. These findings strongly suggest that the 7-nm technology featuring EUV is fully ready for high-volume manufacturing as well as providing a near future logic production with high-quality reliability.

This paper investigates the impact of BEOL design on device and backend reliability - HCI, BTI, EM - due to dependence of self-heating on BEOL in highly-scaled FinFETs. Our analysis indicates that due to poor thermal coupling to substrate - in the thin fin body devices - a large part of heat flows out of BEOL. This makes self-heating, and thus device (FEOL) temperature, very sensitive to BEOL design. The heat flow through BEOL also significantly increases the metal and via temperatures. The increased temperature negatively affects the overall reliability, and one of the ways to mitigate device degradation is optimization of BEOL design.

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V-T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V-T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor-level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V-min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated.

Far-BEOL forming gas anneal has been used to passivate the dangling bonds and to improve the integrity of the gate dielectric [1-2]. The extensive reliability characterization study was conducted on 14nm FinFETs to study the effects of anneals using various gas sources (including high/normal pressure D-2, H-2, and N-2). Despite that high pressure D-2 (HP D-2) anneal gave the best I/O NFET HCI reliability performance, most of the other anneals also provided reasonable and comparable reliability results that can provide as more cost-effective alternate process approach. Product HTOL data using various DOEs demonstrated reliability exceeding 10yrs of life.

Hot carrier injection (HCI) effect with circuits running at very high frequency through overdrive (OD) can manifest under very long stress time and lower temperature where negative bias temperature instability (NBTI) is suppressed. On FinFET technology with presence of self-heating effects (SHE), it is important to decouple the effects to obtain accurate HCI modeling along with right duty cycle for the process wafer level reliability (WLR) requirements and design for reliability (DFR). We'd devised a unique Ring Oscillator (RO) test structure to characterize HCI duty cycle and compare with HCI duty extracted from the RO and IP aging results.