We report an efficient and practical method for accurate design of inductors on Multi-Chip Module (MCM) silicon substrate. The substrate loss was measured and implemented into the model. Both measured inductance and quality factor agree well with simulation. Optimal design of inductors within a finite area is also discussed

It has recently become evident (Davis et al, 1998) that there are many important design and performance advantages to be gained by using a flip-chip silicon-on-silicon MCM (multichip module) architecture for RF applications. This paper describes the structure and assembly of a 1.016 GHz GSM MCM transceiver. In this example, an RF transceiver chip is flip-chip mounted on a circuited silicon substrate which, as part of its circuitry, includes embedded capacitors, inductors and resistors. The resulting flip-chip silicon-on-silicon structure, which is called a “tile” and incorporates all of the RF sensitive nodes, is itself inverted and solder connected to the top side circuitry on a double sided FR-4 laminate substrate. This substrate is furnished with bottom side solder balls for surface mount assembly to, for example, an FR-4 PWB motherboard. Tests of the resulting MCM package showed an exceptionally clean RF resonance peak with none of the spurious resonance peaks that were observed with a transceiver chip of the very same design when enclosed in a conventional leaded package and surface mount soldered to a conventional PWB motherboard. This compact packaging architecture allows for the design and manufacture of optimized MCM packages for RF transceivers that can be as thin as the MCM tile alone

This paper describes a new level of integration and innovation required to meet the integrated circuit (IC)- and system-level challenges of the 21(st) century. We present a technology platform in which chip-scale modules (CSMs) provide greater functionality, higher performance, lower cost, and faster time to market for many of today's emerging products. Our approach is to build CSMs that overcome formidable integration barriers without compromising individual IC technologies. By integrating various IC technologies and their supporting components, we exceed single on-chip performance. Functionality is increased through integration, and performance is improved by maintenance of an on-chip electrical environment. Applications include integrating large blocks of memory with logic, mixing analog and digital IC technologies, and integrating high-frequency ICs with high-quality (high-Q) passive components. The CSM technology platform is poised to unlock the full potential of IC technology and unleash the innovations of designers.

Lumped inductors are very desirable passive components in wireless/RF circuits integrated on MCM substrate. This paper models the inductor from on-wafer high frequency measurement by utilizing the S parameter formulation and exponential gradient method. The S parameter formulation enables us to understand the phase shifting effects within the model while the exponential gradient learning algorithm provides us with a more robust and better fitting technique than the gradient descent algorithm. Both the magnitudes and phases of all S parameters fit well for all the inductors we constructed. It is shown that the phase shifting of the distributed effects should not be neglected even in MCM-D technology. The resulting experimental model provides measurement-verified solid ground for circuit design and numerical characterization.

Integrated passive components are important for high frequency hybrid microelectronics. We have fabricated resistors using reactively sputtered TaN/sub x/ (x<0.5) and Ta/sub 2/Si thin films. We report on the resistivity, temperature coefficient of resistance (TCR), microstructure, composition, and thermal stability as a function of deposition conditions. The resistivity can be tuned, for example, by varying the nitrogen concentration. We have also fabricated capacitors with high capacitance density (70 nF/cm/sup 2/) using Ta/sub 2/O/sub 5/ dielectric films. The Ta/sub 2/O/sub 5/ dielectric films were prepared by various methods such as reactively sputtered Ta/sub 2/O/sub 5/, anodization of reactively sputtered TaN,, and anodization of Ta,Si films. We report on the capacitance density, leakage current, breakdown voltage, and dissipation factor up to high frequencies. We also report on the temperature coefficient of capacitance (TCC) and thermal stability of these capacitors during subsequent processing. A variety of analytical techniques were used to characterize the film properties. These anodic Ta/sub 2/O/sub 5/ capacitors have exceptionally low leakage currents (<1 nA/cm/sup 2/ at 10 V), high breakdown fields (>4 MV/rm), and high capacitance densities (70 nF/cm/sup 2/). The ac measurements of the capacitors showed ideal behavior up to 10 MHz Generally, anodic capacitors degrade upon subsequent processing above 200/spl deg/C due to dielectric and electrode metal interaction. By engineering the dielectric and the electrode materials, we have fabricated anodic Ta/sub 2/O/sub 5/ capacitors that are stable up to 350/spl deg/C with excellent capacitor properties. These capacitors are useful as integrated passive components for advanced packaging applications.

High-Q inductors are the important elements for RF circuit design, especially in the cellular and PCS bands, where they are difficult to be realized. We discuss and explain the current crowding effect, which degrades the Q of the spiral inductor, as the number of turns increases. Both the method of moment (MOM) and the finite-difference time-domain (FDTD) technique are applied to this analysis.

A method of designing low noise amplifier (LNA) using multi-chip module (MCM) technology is described here. First, low noise amplifier blocks using silicon BiCMOS process were fabricated. Noise figure and gain from 2-6 GHz were measured at different bias voltages after chips were fabricated. These chips were designed for multi-chip module integration on a newly developed low cost, low loss silicon substrate on which high-Q matching inductors are fabricated. Since the electrical characteristics of passive components on MCM are well controlled and the electrical characteristics of active devices are measured after fabrication, design accuracy and high yield can be achieved. Two design examples of low noise amplifiers at 2 GHz and 5 GHz are discussed. The 2 GHz LNA design utilizes high-Q spiral inductors as matching components whereas the 5 GHz LNA design utilizes microstrip lines as matching inductors.

Lumped inductors are very desirable passive components in wireless/RF circuits integrated on MCM. This paper, based on the experimental modeling techniques for the extraction of equivalent circuit from measurement, improves the design of MCM inductors by achieving better quality factor and smaller real estate. A Q of 30 is achieved for the common inductors fabricated on MCM substrate. Various inductor design issues are discussed for practical inductor design for wireless applications. Measurement results are presented to demonstrate the high performance achieved through experimental and numerical modeling.

High quality factor (Q) inductors were designed and fabricated on high-resistivity (2000 /spl Omega//spl middot/cm) Si substrates with multichip module (MCM) fabrication technology. A Q-factor of 30 was achieved for an inductor of 4 nH at 1-2 GHz. To enhance the Q-factor and reduce the parasitic coupling capacitance, a staggered double metal-layered structure was utilized by taking advantage of the double-layered metal lines in MCM. With electromagnetic simulation tools, computer-aided analysis was used to optimize the device characteristics. The skin effect and the lossy substrate effect on the performance of the radio frequency (RF) thin-film inductors were studied. The fabrication process used polyimide as the dielectric layer and aluminum as the metal layer. The use of the low dielectric-constant material, polyimide, reduces the parasitic coupling capacitance between metal lines and increases the quality factor and the self-resonant frequency for the RF integrated inductors.

We report high quality (Q) factor inductors fabricated on a high-resistivity (2000 Ω-cm) Si substrate with MCM technology. Q-factors of 30-40 were achieved for inductors of a few nH at 1 GHz

Recently, silicon-on-silicon multichip modules (MCMs) have shifted away from high performance digital applications toward low-end, cost driven products with a primary emphasis on volume production. This shift has been accompanied by changes in the physical structure of the MCM interconnections. Cost reduction has driven them toward thinner metal and dielectric layers, and wherever possible toward the use of fewer layers. It has also fundamentally changed the flip-chip attachment process. We are now reexamining the effect these changes are having on the performance characteristics of the technology, and the role of MCMs in systems packaging.

Semiconductor devices, and in particular InP-based laser devices, are usually bonded on a mounting plate (called a submount or heatsink) or directly onto a package. This bonding assembly, which comprises the die-bonding metallic layers, the joint solder and the submount, serves the purpose of heat dissipator, mechanical support and electrical conductor. As such, the quality of both the bonding metallization and the submount are as important as the device die itself to assure the short- and long-term reliable operation of the electronic assembly. Due to its high thermal conductivity, diamond has been used as a very efficient thermal conductor and dissipator under electronic and photonic devices. This application has become even more attractive since the commercialization of the chemically vapor-deposited (CVD)-diamond, due to its lower cost and larger available surface area compared to natural diamond. Therefore it is only natural to use CVD-diamond as the material of choice for mass production of high-power InP-based laser diode submounts. The device is attached to the submount by a metallic bonding medium that contains a few layers, such as an adhesion layer (typically of titanium (Ti) adjacent to the submount), a barrier layer (typically of platinum (Pt)) and capped with hard solder (such as gold-tin (AuSn) eutectic alloy, which has a melting temperature of 278 °C). While offering optimum bonding conditions, the Ti/Pt/AuSn bonding system provides a high quality bond of the laser diode to the CVD-diamond submount. However, the extensive reaction of the AuSn solder with the Pt and Ti layers, even after short bonding periods of 5–10 s, may lead to mechanical deterioration of the bonded assembly, resulting in delamination of the metal and failure of the bond. This failure occurs mainly due to the thermodynamically reactive nature of the Pt-Sn couple, which reacts almost spontaneously even at room temperature. The reaction consumes the Pt layer and an appreciable amount of Sn, leading to the disappearance of the barrier layer and to dilution of Sn from the solder. The variation in the molten solder stoichiometry results in premature solidification of the solder through the bonding cycle after consumption of the entire Pt barrier layer, and dissolution of the Ti adhesion layer, as well. In order to maintain the good wetting performance of the AuSn solder to the Ti/Pt metals, but yet to improve the thermodynamic stability of the metallurgical bonding system, various other metals such as Ni, W, Cr and some of their alloys were evaluated as advanced alternatives to the Pt barrier layer. The quality of the evaluated metallurgical systems was judged upon wetting performance, thermodynamic stability and lack of premature freezing of the molten solder. The Ti/W/W(Ni3Sn4)/Ni3Sn4/Au multilayered structure was finally defined as the optimal and superior metallurgical scheme for the purpose of bonding laser chip to CVD-diamond submount. The time required until the first surface local freezing phenomenon was observed at the AuSn solder (with eutectic composition of 80 wt.% Au) on Ti/W/W(Ni3Sn4)/Ni3Sn4/Au structure while melted at 320 °C was 200 s, compared to 5–10 s at the Ti/Pt/Au/AuSn system. At the former system the solder was maintained melted at 320 °C for more than 1 h before it was completely frozen, which is much longer than the 30 s measured for the latter system. It was also observed that not only did the AuSn solder on the Ti/W/W(Ni3Sn4)/Ni3Sn4 multilayer maintain its accurate stoichiometric composition through the entire bonding cycle, but it also provided excellent adhesion and integrity for the entire bonded assembly.

We have built and demonstrated a silicon-on-silicon multichip module for use in a cellular telephone. This module performs speaker-dependent voice recognition and also serves as a telephone answering device. It takes advantage of the miniaturization possible with MCM technology. Other important factors in the use of this approach are the fast design and fabrication cycle and the ability to readily integrate specialized CMOS processes into a single package

To address the needs of cost driven, mixed signal applications, we have developed a silicon-on-silicon technology that incorporates both passive and active devices in the module substrate. The technology combines a simple, double-diffused epitaxial bipolar technology with our thin-film MCMs. We describe the basic elements of the technology, typical active device properties and some examples of their use in a low-cost MCM.<>

The realization of a high speed, high-yield flip-chip assembly capability is essential to the development of a practical, cost effective MCM technology because it supports large volume, relatively inexpensive product applications in which equipment costs per unit can be minimized. This paper describes a novel assembly technique for flip-chip silicon-on-silicon Multi-Chip Module (MCM-D) tiles which readily meets the above criteria. This new hybrid technique, which is called AT&T /spl mu/SMT, involves stencil printing a custom AT&T ultra-fine pitch solder paste directly onto a silicon fabric wafer which is then populated with bare die and reflowed, much as surface mount packaged components would be assembled onto a circuit board. This approach is capable of achieving higher component and interconnection densities than can be achieved with any fine-pitch SMT design - and at a lower unit cost at large production volumes than can be achieved with any other MCM assembly technology.