Pass-band insertion loss in low-pass filters implemented in monolithic technologies is mainly limited by the Q of the inductor coils. Furthermore, the size and cost are dominated by the coils. For these reasons, most circuits used in filters of this type are of low order with a minimum number of coils. This paper describes a low pass filter using a bridged-tee architecture to implement a 5th order low pass filter with two attenuation poles at finite frequencies. The circuit is especially well-suited for use in harmonic suppression filters with low pass-band insertion loss. The filter is compared experimentally with a conventional ladder network using two coils. The bridged-tee circuit shows equivalent performance but only requires about 60% of the area of the ladder circuit.

A PLL technique is introduced that enables fast and accurate frequency switching, independent of the loop bandwidth. It uses separate tuning paths, each driving a separate VCO tune port. Different frequencies are produced by letting the VCO make different weighted combinations of the stable tuning voltages. The PLL converges to the stable tuning voltages by switching it a few times between the desired frequencies and tuning paths. Once the stabilized tuning voltages are found, one can switch between frequencies as fast as one can switch between K/sub VCO/s. The technique is applied to a 3.5-GHz integer-N PLL to enable fast jumping of the local oscillator (LO) frequency when an 802.11 transceiver is switched between a low and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CPs), and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filters' charge. The 50-kHz bandwidth PLL achieves a measured 7-MHz jump with /spl plusmn/20 kHz accuracy within 6 /spl mu/s. The measured phase noise is -123 dBc/Hz at 1-MHz offset.

A PLL-technique is introduced to enable fast switching of an 802.11 transceiver local oscillator (LO) between a low-and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CP) and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filter charge. A 50 kHz bandwidth integer-N PLL achieves a measured 7 MHz-jump with /spl plusmn/20 kHz accuracy within 60 /spl mu/s. The measured phase noise is -123 dBc/Hz at 1 MHz offset.

In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used.

We have derived a lumped-element circuit from its coupled line counterpart for a quadrature hybrid coupler. We discuss the uses, design, and characteristics of such circuits in CMOS technology. We show measured characteristics of an example 50-/spl Omega/ 2-GHz coupler with 65 dB of image rejection, 22 dB of directivity, and a 4.7-dB noise figure.

An examination is made of the performance tradeoffs between conventional and superconducting interconnections in applications ranging from printed wiring boards to chips. For most semiconductor-device-based applications, the potential gains in wiring density offered by superconductors are probably more important than the bandwidth improvements. The analysis determines the values of critical current density above which superconductors outperform conventional wires in systems of various physical sizes. The particular interconnection technologies for which high-temperature superconductors show the most promise are thus identified

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

A new differential tuning concept for LC oscillator is introduced and demonstrated on a 4.5GHz CMOS VCO. It uses inductive coupling of varactors, giving highly linear differential tuning with good common-mode rejection. Only one type of varactor is used, allowing the designer to use the varactor-type with the highest C/sub max//C/sub min/ ratio and/or quality factor. It is shown that differential tuning offers a means to suppress the upconversion of common-mode bias noise, allowing for a significant power reduction in the VCO's bias circuitry. The realized VCO combines differential tuning constant K/sub VCO/ is 65MHz/V. The measured phase noise is lower than -124dBc/Hz at 1 MHz offset over the entire tuning range. The circuit, including bias, draws 5.5mA from a 2.5V supply.

We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.

We report an efficient and practical method for accurate design of inductors on Multi-Chip Module (MCM) silicon substrate. The substrate loss was measured and implemented into the model. Both measured inductance and quality factor agree well with simulation. Optimal design of inductors within a finite area is also discussed

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5GHz CMOS VCO. It uses injection-locking through common-mode inductive coupling to enforce quadrature. The technique provides quadrature over a wide tuning range without introducing any phase noise- or power consumption increase. The realized VCO is tunable between 4.6GHz and 5.2GHz and measures a phase noise lower than -124dBc/Hz at 1MHz offset over the entire tuning range. The circuit draws 8.75mA from a 2.5V supply.

The technological trends underlying the application of CMOS technology in wireless applications are leading to the integration of the RF analog functions and the digital baseband processing into a single chip. Two key technical requirements for this integration are the capability to fabricate high Q passive components and the need to maintain electrical isolation between analog and digital components in the resulting mixed-signal chip. Some basic arguments that illustrate the technological conflict between these two important demands are presented, focusing on their implications for the structure of the IC substrate. This structure and the characteristics of the device package play important robs in determining the levels of coupled ground noise that will be present in the mixed-signal IC. A simple, high-level model for coupled ground noise is presented and used to illustrate the impact of design alternatives for the package and for the IC substrate.

This paper presents models for monolithic RF spiral transmission-line baluns. The balun consists of a pair of spiral transformers fabricated on high-resistivity silicon. The lumped-element equivalent models are developed. The second-order or higher order models are synthesized from the first-order lumped model. All lumped parameters for the models are extracted from the real physical structures. Simulated behaviors from the second-order models are in good agreement with the measured results within 10% difference.

We use a stochastic model of the switching current to describe the power spectral density of current noise waveforms induced by digital switching events. We discuss common impedance paths, particularly arising from non-ideal properties of electronic packages, that couple this noise into the substrate of an integrated circuit. We derive estimates of the noise spectrum for modest digital power and typical package characteristics and evaluate the noise in the context of RF mixed-signal designs. Common TQFP packages show significantly worse noise performance than BGA packages with low inductance substrate ground, and are less suitable for demanding applications. The adoption of differential design methods can eliminate this source of common-mode noise, at the expense of added power or higher noise figure

We discuss the design of coupled spiral transmission line baluns modeled after the Marchand type. The balun structure consists of a pair of coupled spiral conductors vertically offset across intervening polyimide layers, The baluns are fabricated on various substrates (glass and high- and low-resistivity silicon). The characteristics such as return loss, insertion loss, and output signal imbalance are measured. The center frequencies of 3-dB bandwidths (BW's), primarily determined by their conductor lengths, range from 1.2 to 3.5 GHz, The 3-dB BW normalized by the center frequency is similar to 1.48 in all cases. We observe an optimum BW for better performance. Return losses at the center frequencies range from 13 to 18 dB, Amplitude imbalance distributes in the range of 0.3-1.0 dB, depending on the sizes of devices and substrates, The minimum insertion loss is 0.55 dB for the balun on a glass substrate with 100-mu m-wide conductors. The devices fabricated on glass and high resistivity (>4000 Omega.cm) silicon show remarkably similar behaviors despite the large difference in dielectric constant. This technique is applicable to monolithic microwave integrated circuits.

We describe a design method and lumped model for a circular spiral transmission-line balun. All lumped values are extracted from the geometric parameters of the balun. From simulation, the design parameters with well predicted characteristics are defined. The balun is fabricated using multi-chip module processing technology, which is suitable for integration in RF packages. Measurements show a wide bandwidth of 1.5-4.1 GHz and excellent balanced outputs. Amplitude imbalance less than 0.5 dB and phase imbalance less than 4/spl deg/ are achieved. The simulation results are compared with the measurement. The model captures all important properties of the balun with reasonably high accuracy.

We will discuss the operating principles, design, fabrication and measured properties of an inductively coupled monolithic spiral transformer Devices like this one can be integrated into module substrates, and are practical for RF wireless applications operating at frequencies above several hundred MHz. The common model for a transformer is a pair of mutually coupled inductors. At high frequencies, however, capacitive coupling between the windings leads to non-ideal behavior and resonance, limiting the device's useful operating range. We show that the wide-band characteristics of transformers is closely related to that of coupled transmission lines, and we can rake advantage of this feature to obtain good transformer behavior at higher resonant modes.

In this work, a spiral transmission line balun has been fabricated on a high resistivity silicon substrate. The Marchand-type balun has been designed to have the same physical common ground points for the output transmission lines, which eliminates imbalance due to potential difference at the ground. Return loss is better than 17 dB in the frequency band of 1.6-4.1 GHz, especially 39 dB around 1.9 GHz. The amplitude imbalance is less than 0.3 dB throughout the bandwidth. The phase departure from 180/spl deg/ is less than 20 over the frequency range of 1.6-2.6 GHz. The balun is suitable for MMIC application.

It has recently become evident (Davis et al, 1998) that there are many important design and performance advantages to be gained by using a flip-chip silicon-on-silicon MCM (multichip module) architecture for RF applications. This paper describes the structure and assembly of a 1.016 GHz GSM MCM transceiver. In this example, an RF transceiver chip is flip-chip mounted on a circuited silicon substrate which, as part of its circuitry, includes embedded capacitors, inductors and resistors. The resulting flip-chip silicon-on-silicon structure, which is called a “tile” and incorporates all of the RF sensitive nodes, is itself inverted and solder connected to the top side circuitry on a double sided FR-4 laminate substrate. This substrate is furnished with bottom side solder balls for surface mount assembly to, for example, an FR-4 PWB motherboard. Tests of the resulting MCM package showed an exceptionally clean RF resonance peak with none of the spurious resonance peaks that were observed with a transceiver chip of the very same design when enclosed in a conventional leaded package and surface mount soldered to a conventional PWB motherboard. This compact packaging architecture allows for the design and manufacture of optimized MCM packages for RF transceivers that can be as thin as the MCM tile alone

We show an example design of a cellular telephone that demonstrates the marked contrast between passive component usage in its base-band and radio sections. We discuss the performance demands that applications like these place on passive components and how these demands relate to the technology used to build the components. Recently, we have demonstrated and reported on the use of silicon-on-silicon thin film modules to integrate the tank resonator circuit of the 1 GHz UHF VCO in a GSM transceiver. We discuss some of the ways that these results can be extended to take further advantage of component integration. A unique characteristic of modules used in RF applications is the integration of thin-film spiral inductors. One of the concerns in the tight integration of these components is crosstalk arising from mutual inductive coupling between components. We have calculated the mutual inductive coupling between spiral inductors, with and without ground planes, and present representative examples from typical module designs