The design of integrated binary and matched capacitor fields is described. A module generator for spiral symmetric inductors is presented. In addition the generator creates an appropriate spectre description automatically in order to simulate and optimize the inductor. Finally the machine-aided layout construction of precision resistors is depicted. All presented module generators are technology-independent due to the use of the MOGLAN library [5, 6]. (Abstract)

A novel CMOS operational amplifier with two differential stages has been fabricated and has been measured successfully. A nested Miller compensation is used to ensure a stable operation. The layout has been created automatically by using the ALADIN tool. An appropriate smallsignal model is depicted for the amplifier and the measurement results are presented.

The design of a complementary folded-cascode operational amplifier with rail-to-rail input range for low voltage operation is described. Due to the biasing transistors M-16 and M-19 the output swing is increased. By using the ALADIN tool [5-7] the layout has been created automatically. Prototype circuits have been fabricated with a 0.25 mu m CMOS technology and the measurements of the amplifier are presented.

The design of an integrated CMOS cascoded operational amplifier with two differential input stages is described. By using the nested Miller compensation the stability of the operational amplifier is ensured. The layout has been created automatically by using the ALADIN tool [6–9] and prototype circuits have been fabricated. The small signal model for the amplifier is depicted and the test results are presented.

In this paper the design of a CMOS cascoded operational amplifier is described. Due to technology scaling the design of a former developed operational amplifier has now overcome its stability problems. A stable three stage operational amplifier is presented. A layout has been created automatically by using the ALADIN tool. With help of the extracted layout the performance data of the amplifier is simulated.

This paper presents an extension of ALADIN for approximately calculating the current density and heat distribution of analog circuits. The tools are integrated into the ALADIN package, which allows designers to create analog circuit layouts automatically. The optimization is speeded up and the reliability of the design is improved. The benefit of ALADIN is demonstrated with the design of a linear power amplifier with ±1.5V power supply.

The shortcomings of conventional separate placement and global routing becomes more prevalent for analogue integrated circuits that often involve complex constraints. The paper presents a novel two-stage placement technique to solve the analogue macro-cell placement problem. The entire placement procedure is divided into global placement and detailed placement. During the global placement, a hybrid genetic placement approach using a half-perimeter net-length estimator is employed. It perforrns a rough and quick search to locate the region of the optimum. In the detailed placement, a very fast simulated re-annealing placement approach and a minimum-Steiner-tree-based global routing are performed simultaneously. In this way, the optimum can be found by searching a relatively small region. The experiments show this promising algorithm, which provides the satisfactory results comparable to expert manual placements, can help generate higher quality layouts than conventional approaches.

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.

In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time.

Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines.

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit-matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide-based flat scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation-decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. Copyright © 2005 John Wiley & Sons, Ltd.

This work presents a layout synthesis tool for analog integrated circuits called Aladin. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators for sub-circuits. A two-stage placement technique is proposed, which dramatically improves the placement accuracy without compromising the efficiency compared with the one-stage placement. The analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. The benefit of Aladin providing layouts comparable to expert manual ones is demonstrated with several existing tools.

This paper presents a novel approach to analog module placement with genetic algorithm. The bit matrix encoding is employed to improve search efficiency. It uses the principle of the divide and conquer technique, which allows the genetic algorithm to generate new configurations faster without degrading its search result. The idea of module slide is adopted to transform the absolute placement to the relative placement. It drastically decreases the configuration space without degrading search opportunities. Inspired by natural phenomena, similarity checks between the mating parents and between either parent and offspring are performed to improve the quality of evolution. They prevent the search from premature during the reproduction. The dedicated cost function covers the special requirements of analog integrated circuits. A fractional factorial experiment is conducted using an orthogonal array to study the algorithm parameters. A meta GA is applied to determine the optimal parameter values. The fractional factorial experiment shrinks the configuration space so that the meta GA can complete a search more efficiently. The Algorithm with optimized parameters is tested with several local benchmark circuits. The experimental results show this promising algorithm makes the better performance than the conventional simulated annealing approach with the satisfactory results comparable to manual placement. It considerably improves the design efficiency.

In this paper a new programmable sensor interface circuit for contactless inductive position sensors is described, which is based on a novel measurement method. The chip meets the requirements of various sensors with different electrical and mechanical parameters. The interface circuit is fabricated in a 0.8μm CMOS technology. It has a resolution of 11 bits for the position information, which is validated by measurements.

This paper presents an automatic layout design system for analog integrated circuits. It is tailed for analog circuit designers so that they can bring their special knowledge and experience into the synthesis process to create high quality layouts. Designers can write and maintain their own technology and application independent module generators for subcircuits in a module generator environment. Different from other systems, layout generation is based on optimal complex modules rather than simple single devices. A novel genetic placement approach with simulated annealing is developed. The minimum-Steiner-tree based global routing can be integrated into the placement procedure in order to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. Several examples are given to demonstrate its design efficiency and usability. Experiments show that it is superior to the existing tools and can provide comparable results to manual layouts.

This paper presents a novel genetic algorithm for analog module placement based on ageneralization of the two-dimensional bin packing problem. The genetic encoding and operators assure that allproblem constraints are always satisfied. Thus the potential problems of adding penalty terms to the costfunction are eliminated so that the search configuration space is drastically decreased. The dedicated costfunction is based on the special requirements of analog integrated circuits. A fractional factorial experimentwas conducted using an orthogonal array to study the algorithm parameters. A meta GA was applied todetermine the optimal parameter values. The algorithm was tested with several local benchmark circuits. Theexperimental results show that the algorithm has better performance than the simulated annealing approachwith satisfactory results comparable to manual placement. This study demonstrates the effectiveness of thegenetic algorithm in the analog module placement problem. The algorithm has been successfully used in alayout synthesis tool.