Presents a short description of patents in the solid-state circuits industry and includes patent numbers, dates file, inventors, and assignee.

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

We present efficient MOS-capacitor based silicon photonic modulators driven by low-power CMOS inverter based driver ICs. Operating under the lumped-element approximation, modulation formats of NRZ, PAM, and QAM are demonstrated.

The design of a continuous rate octal 1.0 to 3.2 Gb/s serializer/deserializer circuit that meets SONET and XAUI requirements is presented. The performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications. This is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0.13 /spl mu/m digital CMOS technology, the part exhibits less than 5 mUI r.m.s. jitter and the 1.2 mm/sup 2/ transceiver dissipates 160 mW.

The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards.

This paper describes a CMOS line driver that operates from a 3 V power supply and delivers a peak current of about 100 mA to the load. The novel features of the circuit are high power efficiency, an output pulse shape and amplitude independent of power supply and temperature variations, and the ability to handle abnormal load termination conditions. The circuit has been designed in a 0.9 /spl mu/m CMOS technology and does not require any low-threshold devices.

This paper describes the design of a baseband processor for IS-54 North American cellular telephony standard. The effect of diverse circuit impairments on the error vector in digital mode and on the parasitic amplitude modulation in analog mode are analyzed. An analog offset compensation scheme, which takes advantage of the TDMA operation, is presented. The device incorporates a Manchester data decoder for data transmission in analog mode. The messages can be sent via two interfaces to the DSP or mu-processor. The architecture of the digital signal processing chain is discussed. The device is fabricated in a 0.9 mu CMOS technology with an area of 40 mm(2).

A 5 V CMOS chip providing the D/A, A/D, filter, and a programmable gain amplifier (PGA) for HDSL and ADSL is described. The chip includes 12-bit, 10 Msample/sec converters, filters, and a PGA having 48 dB gain with 1.7 MHz bandwidth. This chip is used in an E1-rate (2.048 Mbps) ADSL transceiver achieving a bit error rate of less than 10-9 over 5.4 km of 0.4 mm twisted copper wire

This paper describes the low-power techniques used to design the Clock/Data recovery, Jitter Filter and the high current Line Driver circuits in a Quad Line Interface for DS1/CEPT applications.

A base-band modem/codec chip for the dual-mode North American IS-54 standard is shown. In the digital mode of operation, this chip acts as a modem. On the transmit side, it performs pi /4-shifted DQPSK modulation, square-root raised-cosine filtering, and waveform synthesis. The receive section helps to demodulate the signal by minimizing the intersymbol interference using square-root raised-cosine filters. In the analog mode of operation, the chip behaves like a codec. The transmit section supports part of the frequency modulation process while the receive section acts as an analog-to-digital interface. In addition to integrating the signal-processing sections of the transmit and receive paths, the chip also offers auxiliary controls for such functions as automatic gain control, automatic frequency control, and transmit power control. A wideband data detector is provided to decode the Manchester-encoded forward analog control channel messages in stand-by mode or forward analog voice channel messages.<>

This paper describes the design of a baseband codec for European and North American digital cellular telephone applications. By integrating all the data conversion circuitry, this chip offers a low-cost, low-power solution to base-band signal processing and control functions. The receive section has two paths to process the in-phase and quadrature-phase components of the signal. Each path consists of a programmable gain amplifier (PGA) and a 10-b sigma-delta A/D converter. Two 8-b D/A converters, generate the in-phase and quadrature-phase components of the transmit signal. A 9-b DAC and a 10-b DAC are provided to perform auxiliary control functions. The chip is fabricated using a 0.9-mu-m CMOS technology and has an area of 21 mm2. The average power dissipation is 85 mW.

A five channel analog front-end processor for a frequency division multiplexed (FDM) system is described. Each channel has a low-noise, two stage programmable-gain amplifier with a gain range of 15-35 dB in 1 dB steps, followed by a fifth-order elliptic switched-capacitor low-pass filter with a band edge of 300 kHz. A four-input amplifier has been designed for the first gain stage. This achieves fully balanced gain with a high input impedance. An exact design technique has been used to realize the filter. An analog multiplexer time-multiplexes the five channels with a crosstalk suppression of better than 70 dB. The chip also has a microprocessor interface, and timing and control circuitry. Fully differential topology has been used to obtain a dynamic range of 70 dB, signal-to-distortion ratio of 68 dB, and a power supply rejection ratio of 85 dB. The chip uses a 2.25 μm gate-length, 5 V technology, and has a power dissipation of only 390 mW

A novel scheme for generating multiple reference voltages for pipeline A/D conversion is proposed. The basic idea is to develop the required reference voltages by summing the voltages from two reference voltage banks. This scheme has potential for high-speed conversion. Further, the architecture of the resistor network which forms the two voltage banks, offers a wide trade-off in power dissipation...

In a recently published paper by K.R. Lakshmikumar, et al. (see ibid, vol.SC-21, no.6, p.1057-66, 1986) the yield of a digital-to-analog converter (DAC) as a function of component matching is estimated analytically. Here, an assumption inherent to that derivation, namely that the DAC outputs are independent, is questioned and is demonstrated to be inconsistent with Monte-Carlo simulations. The rep...

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of ...

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.