Persistent memory has emerged as a groundbreaking solution for byte-addressable storage-class memory (SCM). While persistent memory is highly desirable due to its advantages in high capacity, performance, and cost-effectiveness, novel system architecture solutions are required for its adoption in data center applications that demand high performance and reliability. The major challenges are issues related to persistent memory media, such as endurance, retention, and reliability, along with hardware and software system integration within the data center platform. To reduce the total service cost for end users by utilizing persistent memory media as the main memory, we have developed a comprehensive system comprising persistent memory chips, a persistent memory controller, firmware, and system software layers that effectively mitigate persistent memory issues and are compatible with data center applications. In this paper, we discuss the system design of a high-performance byte-addressable persistent memory with a Compute Express Link (CXL) interface. This design choice was based on real-world persistent memory limitations. It was implemented on Application-Specific Integrated Circuit (ASIC) platform, and tested on in-memory database (IMDB) applications. Bandwidth and latency results show that our design approach for CXL persistent memory offers comparable performance to CXL dynamic random access memory (DRAM) under certain test cases while providing increased memory capacity and reduced cost. Our main contributions are summarized as follows: (1) We have conducted a systematic study on persistent memory media issues and have proposed a hardware and software architecture that ensures reliable and efficient utilization of persistent memory media. Media management algorithms for endurance, disturbance, retention, and drifting have been developed and validated. (2) We have pioneered the first SCM-based data-center CXL memory. By utilizing the CXL interface, the barrier to adapting persistent memory to server platforms in data centers has been largely reduced, as it uses Peripheral Component Interconnect Express (PCIe) interconnect slots instead of a limited number of DIMM slots. Our persistent memory solution with the CXL interface offers enhanced compatibility across various platforms and unlocks the potential for memory pooling. (3) We have developed a software path that integrates persistent memory into our server systems, spanning from the application layer to the driver and firmware layers. To evaluate its performance, we have conducted benchmarking tests using in-memory databases as the application and compared the results with those of CXL DRAM devices and Intel's Optane product.

The exponential growth in demand for high-performance computing systems has created an urgent requirement for innovative memory technologies that can provide higher bandwidth and enhanced capacity scalability. In particular, Compute Express Link (CXL) has emerged as a promising solution for memory expansion and system acceleration. Hash-based index structures are widely recognized as fundamental components of in-memory database systems, and they are commonly used for indexing in-memory key-value stores due to their capability for rapid lookup performance. How to design and maintain a hash index structure in a CXLbased disaggregated memory system, with comprehensive consolidation, is a challenging topic of in-depth research. Specifically, the architecture and characteristics of the CXL memory device are significantly distinct from those of DRAM and PMEM. Simply applying prior hashing approaches without considering the differences would not fully exploit the characteristics presented by CXL memory devices. This leads to the performance inefficiencies of conventional indexing designs and operation processes that overlook the characteristics of the CXL memory device. In this paper, we conduct extensive experiments on two real CXL memory devices based on the 4thgeneration Intel® Xeon® Scalable Processor with CXL 1.0 support. Specifically, we run various microbenchmarks not only to evaluate the performance characteristics of CXL memory devices, but also to measure the performance impact of different memory allocation methods. We observe significant performance disparities and allocation inefficiencies, motivating us to innovate the hash design in the CXL-based disaggregated memory system. Upon in-depth analysis, we propose CHash, as shown in Figure 1, which consists of several key designs, as shown below: Stage buckets for KV batching. The experimental results show that real CXL memory devices from different vendors exhibit diverse performance characteristics. Moreover, there is still a significant performance gap between CPU-attached DRAM and CXL memory. To address this difference, CHash first stores the KV records in a DRAM buffer, called the stage bucket in our design, to batch the KVs, avoiding frequent and small writes to CXL memory devices. SAcceleration techniques for fast lookups. Although memory access latencies for read and write operations are comparable, the end-to-end performance of reads is lower than that of writes due to multiple caching layers, including the CPU cache and the write buffer in the device's memory controller, shorten the write latency. In response, CHash implements several acceleration techniques designed to minimize costly key-value comparisons, thereby reducing the number of reads to CXL memory. Furthermore, CHash stores the metadata which is the most frequently accessed components of the hash table in DRAM to enhance the overall performance. Some alternative optimizations for the effective CXL memory management, including two-level filtering, hash multiplexing and so on, are also further adopted to improve the overall performance. Extensive experimental results validate the efficiency of CHash in different CXL memory devices, demonstrating that it achieves a 2.2× to 9.4× speedup for insertions, and a 1.2× to 4.5× speedup for lookups, all the while maintaining a high load factor (~90%), compared to state-of-the-art hashing schemes.

Recent breakthroughs in medical AI have proven the effectiveness of deep learning in fetal echocardiography. However, the limited processing power of edge devices hinders real-time clinical application. We aim to pioneer the future of intelligent echocardiography equipment by enabling real-time recognition and tracking in fetal echocardiography, ultimately assisting medical professionals in their practice. Our study presents the YOLOv5s_emn (Extremely Mini Network) Series, a collection of resource-efficient algorithms for fetal echocardiography detection. Built on the YOLOv5s architecture, these models, through backbone substitution, pruning, and inference optimization, while maintaining high accuracy, the models achieve a significant reduction in size and number of parameters, amounting to only 5%-19% of YOLOv5s. Tested on the NVIDIA Jetson Nano, the YOLOv5s_emn Series demonstrated superior inference speed, being 52.8-125.0 milliseconds per frame(ms/f) faster than YOLOv5s, showcasing their potential for efficient real-time detection in embedded systems.

Memory semantic Solid State Drives (MS-SSDs) provide a promising opportunity to enable the hybrid memory architecture (HMA). The memory semantic interface enables the CPUs to directly access structured data in SSDs and eliminate bulk data copy/swap between the memory and storage devices. However, existing hash indexings issue many random writes, resulting in two problems when directly deployed on MS-SSD-based HMA: 1) Highly random traffic persisted to the underlying NAND flash of MS-SSDs incurs significant garbage collection (GC) overhead. 2) Placing frequently updated memory pages of hash indexings in persistent memories (PMs) is anticipated to reduce write latency, failing to work effectively due to the lack of skewness. To address the above problems, we propose a novel MS-SSD-friendly hash indexing scheme called TieredHM. It employs a multi-layer structure and opportunistic data movement (ODM) to construct skewed writes. Hence, the MS-SSD can transform the writes into multi-streamed writes, separating data with different update frequencies to reduce GC overhead. Besides, since the top layer is updated much more frequently (more skewed) than other layers, placing the top layer of TieredHM into persistent memory can significantly reduce write latency. TieredHM further leverages a prefetch mechanism based on the internal parallelism of NAND flash to reduce search overhead incurred by ODM. Experimental results show that TieredHM reduces the average write latency and GC overhead by up to 8.3X and 20.0X compared to state-of-the-art hash indexings without sacrificing read performance.

NVMe zoned namespace (ZNS) SSDs present a new class of storage devices with attractive features including low cost, software definability, and stable performance. However, one primary culprit that hinders the adoption of ZNS is the high garbage collection (GC) overhead it brings to host software. The ZNS interface divides the logical address space into size-fixed zones that must be written sequentially. Despite being friendly to flash memory, ZNS requires host software to perform out-of-place updates and GC on individual zones. Current ZNS SSDs typically employ a large zone size (e.g., of GBs) to be conducive to die-level RAID protection on flash memory. This impedes flexible data placement, such as mixing data with different lifetimes in the same zone, and incurs sizable data migrations during zone GC. To address this problem, we propose FlexZNS, a novel ZNS SSD design that provides reliable zoned storage allowing host software to configure the zone size flexibly as well as multiple zone sizes. The size variability of zones poses two interrelated challenges, one for the SSD controller to establish per-zone RAID protection, and the other for host software to manage variable zone capacity loss caused by parity storage. To tackle the challenges, FlexZNS decouples the storage of parity from individual zones on flash memory and hides the zone capacity loss from the host software. We verify FlexZNS on a ZNS-compatible file system F2FS and a popular key-value store RocksDB. Extensive experiments demonstrate that FlexZNS can significantly improve the system performance and reduce GC-induced write amplification, compared with a conventional ZNS SSD with large-sized zones.

NAND flash-based Solid State Drives (SSDs) provide a promising opportunity to enable the unified memory-storage hierarchy (UMH). The UMH renders a single memory address space for heterogeneous memories. Thus, the CPUs can directly access structured data in SSDs and eliminate bulk data copy/swap between the memory and storage devices. However, applying traditional indexing structures directly on SSDs may lead to poor performance. Particularly, the popular hash indexing generates highly randomized write traffic, incurring significant garbage collection overhead in SSDs. To address this problem, we propose a novel SSD-friendly hash indexing scheme called Tiered Hashing. It employs a multi-layer structure and opportunistic data movement (ODM) to construct skewed writes. Hence, the SSD can transform the writes into multi-streamed writes, where hot and cold data are separated to reduce GC overhead. Experimental results show Tiered Hashing reduces the average write latency and GC overhead by up to 94.98% and 90.71% compared to state-of-the-art hash indexings, without sacrificing read performance.

NAND flash-based Solid State Drives (SSDs) provide a promising opportunity to enable the unified memory-storage hierarchy (UMH). The UMH renders a single memory address space for heterogeneous memories. Thus, the CPUs can directly access structured data in SSDs and eliminate bulk data copy/swap between the memory and storage devices. However, applying traditional indexing structures directly on SSDs may lead to poor performance. Particularly, the popular hash indexing generates highly randomized write traffic, incurring significant garbage collection overhead in SSDs. To address this problem, we propose a novel SSD-friendly hash indexing scheme called Tiered Hashing. It employs a multi-layer structure and opportunistic data movement (ODM) to construct skewed writes. Hence, the SSD can transform the writes into multi-streamed writes, where hot and cold data are separated to reduce GC overhead. Experimental results show Tiered Hashing reduces the average write latency and GC overhead by up to 94.98% and 90.71% compared to state-of-the-art hash indexings, without sacrificing read performance.

In large-scale cloud storage systems, Solid-State Drive (SSD) has been broadly used as the mainstream storage device because it has the advantages of low access latency and high throughput. However, conventional SSD is a black-box system to host softwares, thus failing to fully exploit the benefits of NAND flash and provide high quality of service (QoS). On the other hand, Open-Channel SSD (OCSSD) which exposes its internal information to the host software, has the potential to solve this problem. However, existing OCSSD fails to achieve anticipated performance under heavy workloads. To this end, we propose an advanced OCSSD-based driver developed with the novel data placement policy, redefined garbage collection (GC) with copyback technique, efficient prefetch read scheme, and fast live upgrade method. Our work describes the consistent efforts to pursue high performance and QoS in OCSSDs with different approaches. The evaluation results show that our novel Open-Channel SSD is able to provide high I/O throughputs and predictable I/O latencies. For example, our Open-Channel SSD can improve I/O throughputs by 103% and reduce the 99th percentile latency by 62.9% on average compared with the state-of-the-art NVMe SSDs.