In this paper, we propose a technique of predicting the execution time of PLC application programs written in relay ladder logic. The proposed technique divides an RLL program into several RLL blocks and then transforms them into boolean logic equations. The internal states of an RLL program is analyzed and their dependencies are used as constraints when we solve the boolean logic equations. The plant information represented by exclusiveness of input contacts is also used as constraints. The constraint analysis reduces the complexity of logic programming as well as the worst-case timing prediction. The algorithm for partitioning variables in the logic equations is developed to reduce the complexity further.

The paper presents a modeling and simulation method to evaluate the performance of distributed computer control systems (DCCSs). Task response time, resource utilization, and network delay are considered as performance indices for time critical systems. The proposed DCCS model is composed of nodes, network, and environment model and their sub models are also described. The suggested method is applied to the DCCS of CAL (Continuous Annealing Line) in a steel plant and a new DCCS with an open network, in order to estimate the sustain performance.

This paper presents a technique of calculating the worst-case execution time of PLC application programs written in relay ladder logic. The concept of generic PLC and RLL block is introduced to develop a system-independent prediction algorithm. The technique divides an RLL program into several RLL blocks and then transforms them into Boolean logic equations. The internal states of an RLL program is analyzed and their dependencies are used as constraints when we solve the Boolean logic equations. Since the time for solving Boolean logic equations increases exponentially as the number of independent variable increases, the algorithm for partitioning variables in the Boolean logic equations is also developed.

In this paper, a memory-based Petri net implementation is discussed. To realize a memory-based implementation, a sub-class Petri net model is suggested. The suggested model, B-Petri net, is a marked graph whose numbers of input places and output places of a transition are limited to two. The B-Petri net has the same modeling power as a marked graph. The complexity of the B-Petri net is analyzed, and the hardware implementation architecture of a programmable controller based on it is also suggested. The memory tables have realizable memory size, and they are reduced well in case of some real applications like a programmable controller