In ubiquitous networking environments, we generally need two or more heterogeneous communication systems coexisting in a single place. Especially, wireless local area networks (WLANs) based on IEEE 802.11b specifications and wireless personal area networks (WPANs) based on IEEE 802.15.4 specifications need to coexist in the same Industrial, Science and Medial (ISM) band. If the WPAN communication coverage is expanded using a cluster-tree network topology, then the 802.15.4 network is more susceptible to interference from neighboring WLANs. In this paper, we propose an adaptive transmission power aware cluster scheduling algorithm using multiple channels in a WPAN in the presence of WLAN interference. The algorithm includes node identification, channel allocation, clustering and time scheduling. To evaluate the performance of the proposed algorithm, the performance metrics such as Bit error, Throughput, Average End-End Delay and Average Jitter is measured through Qualnet simulation. The measurement result shows that the proposed algorithm is effective in an IEEE 802.15.4 cluster-tree network in the presence of multiple IEEE 802.11 interferers.

The design of efficient routing protocols for Ad hoc networks is a complex issue. These networks need efficient algorithms to determine ad hoc connectivity and routing. MANET aims not only to provide correct and efficient routes between pair of nodes but also to provide energy efficient route to maximize the life time of ad hoc mobile networks. In this paper, a dynamic energy conscious routing algorithm ACE-AODV where cross layer interaction is provided to utilize the energy related information from physical and MAC layers. This algorithm avoids the nodes which are having low residual energy. By maximizing the lifetime of mobile nodes routing algorithm selects a best path from the viewpoint of high residual energy path as part of route stability. The RTS/CTS transmission is a crucial step towards saving the energy of mobile nodes. The SINR value is also considered in the path selection. Directional antenna adds to the system, increased throughput and improved channel reuse. The receiving power of sender,

This chapter considers LQ optimal controls for input and state delayed systems. The control structures of LQ optimal controls are free without any prior requirements, while control structures of non-optimal stabilizing controls and guaranteed cost controls in previous chapters are given a priori in feedback forms with unknown gain matrices. Finite horizon controls are dealt with first. Due to the inherent requirement of infinite horizons associated with stability properties, infinite horizon controls are obtained by extending the terminal time to infinity, where their stability properties with some limitations are discussed. Then for general stabilizing feedback controls, receding horizon LQ controls, or model predictive LQ controls, are obtained from finite horizon controls by the receding horizon concept, where their stability properties are discussed with some cost monotonicity properties. For input delayed systems, two different finite horizon LQ controls are obtained, one for a predictive LQ cost containing a state predictor and the other for a standard LQ cost containing a state. The former is obtained for free and also fixed terminal states due to the simple reduction transformation while the latter only for free terminal states. From the finite horizon LQ controls, infinite horizon LQ controls are obtained and discussed with stability properties and some limitations. Receding horizon LQ controls are obtained from the above two different finite horizon LQ controls for input delayed systems. Cost monotonicity conditions are investigated, under which the receding horizon LQ controls asymptotically stabilize the closed-loop system. For state delayed systems, three different finite horizon LQ controls are obtained, one for a simple cost, another for a cost including a single integral terminal term, and the other for a cost including a double integral terminal term. The solution is shown to be more complex as a cost becomes more complex. From these finite horizon LQ controls, infinite horizon LQ controls are obtained and discussed with stability properties and some limitations Receding horizon LQ controls are obtained from these finite horizon LQ controls for state delayed systems. Cost monotonicity conditions are investigated, under which the receding horizon LQ controls asymptotically stabilize the closed-loop system. It is shown that receding horizon LQ controls with the double integral terminal terms can have the delay-dependent stability condition while those with the single integral terminal terms have the delay-independent stability condition. Since these receding horizon controls are still complicated, simple receding horizon LQ controls are sought with a simple cost or with a short horizon distance.

We address a class of systems for which the solution to an H-infinity optimal control problem can be given on a very simple closed form. In fact, both the control law and optimal performance value are explicitly given. The class of systems include models for large-scale systems such as temperature dynamics in buildings, buffer networks and transportations systems. Furthermore, the structure of the control law is suitable for distributed control of such large-scale systems, which is illustrated through examples.

Network Simulator (NS) is a discrete event simulator targeted at networking research that provides substantial support for simulation of various networks. Performance evaluation in effective manner is the main concern of this paper. This paper, presents a mathematical model to work with the pre-simulation TCL file and post-simulation trace file evaluation for the 802.15.4 networks. The impact of BO and SO on performance of 802.15.4 with varying duty cycle is analyzed considering various parameters like packet delivery ratio, average end-to-end delay and energy consumption in different state: receiving, transmitting and idle mode.

This chapter considers output feedback stabilizing controls for time-delay control systems with single input delays and single state delays. Constant delays are dealt with mainly but time-varying delays are also dealt with in addition when necessary. For output feedback stabilizing controls for input delayed control systems, the Smith predictor method is first introduced briefly due to its historic importance. The advantages and drawbacks of the Smith predictor method are discussed. Then a Luenberger-type observer and a dynamic output feedback control are introduced combined with the reduction transformation so that they can be handled via ordinary system approaches. For output feedback stabilizing controls for state delayed control systems, the Luenberger-type observers are first introduced, combined with state feedback controls. Then dynamic output feedback stabilizing controls are obtained, based on Razumikhin, Lyapunov–Krasovskii, and cascaded delay system approaches. Some results based on the Krasovskii theorem are extended to systems with time-varying delays with and without bounded derivatives. Robust output feedback stabilizing controls for state delayed control systems with model uncertainties are obtained based on the Krasovskii theorem and the cascaded-delay system approach. Some results based on the Krasovskii theorem are extended to systems with both model uncertainties and time-varying delays with and without bounded derivatives.

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

For highly scalable NAND flash memory applications, a compact (4F(2)/cell) nonvolatile memory architecture is proposed and investigated via threedimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction (especially below 20mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power consumption. (C) 2015 The Japan Society of Applied Physics

Abstract: This article introduces recent trends in RHC (Receding Horizon Control), also known as MPC (Model Predictive Control), that has been well recognized in industry and academy as a systematic approach for optimal design and constraint management. Constrained and robust RHCs will be briefly reviewed with milestone results. Among the diverse developments and achievements of RHCs, implementation issues will be focused on, together with the latest applications. In particular, this article introduces results on how to solve a finite horizon open-loop optimal control problem in an efficient way, together with code generation for real-time execution and easy implementation. Instead of traditional applications such as refineries and petrochemical plants, this article highlights some selected emerging applications, such as energy management systems and mechatronics, that have resulted from state-of-the-art high performance computing power and advanced numerical schemes.Keywords: RHC (Receding Horizon Control), MPC (Model Predictive Control), constraint handling, robust, computation, implementation

A simple electromechanical diode nonvolatile memory (NVM) cell design was recently proposed and demonstrated to be well suited for implementation in a cross-point memory array architecture. In this paper, a scaling methodology for this new NVM technology is developed with the aid of a calibrated analytical model. A nanoelectromechanical NVM cell (with 20-nm minimum feature size) is projected to operate with voltages below 2 V and sub-1-ns programming time.

: Historically, our society requires computational memory media to support the development of our civilization. It is likely that our society will keep demanding larger capacity memory. However, conventional memory technologies are facing many challenges such as difficulties of miniaturization and guarantee of good reliability. For this reason, alternate memory device designs are proposed to overcome the conventional memory device technologies. For DRAM technology, a double-gate array having vertical channel structure (DGVC) with 4F2 cell size is proposed, which can be fabricated on a bulk silicon wafer using the conventional memory process flow for stand-alone DRAM application. The operation and scalability of the DGVC cell are demonstrated via TCAD device simulations. For Flash Memory technology, a new backside charge storage non-volatile memory (BCS-NVM) cell design is proposed. A NAND flash array of the BCS-NVM cells can be fabricated on a modified SOI substrate. TCAD device simulation show that this design allows for a relatively high cell read current and steep sub-threshold slope to enable lower voltage operation in comparison with conventional NAND flash memory devices. As a new concept of non-volatile memory technology, a nano-electro-mechanical (NEM) diode non-volatile memory cell design is proposed. This design eliminates the need of a selector device to form a cross-point array, by leveraging the gap closing actuator. The electro-mechanical diode cell design can be scaled to 20 nm minimum lateral dimension by following an appropriate scaling methodology in consideration of various practical and fundamental limits. Low-voltage ( 2 V) and high-speed (sub-nanosecond) operation are projected using a calibrated analytical model as well as 3-D FEM simulation. These findings indicate that electro-mechanical diode technology is promising for high density storage beyond the limits of conventional flash memory technology.