To consider STT-MRAM as an SRAM replacement, the reliability of the MTJ devices has to be demonstrated. A comprehensive study of degradation of STT-MRAM magnetic tunnel junction barrier under stress is presented in this paper. It is found that the breakdown mechanism of such devices follows a consistent path of soft breakdown (SBD) followed by hard breakdown (HBD). We discuss the strategy to improve the write margin by reducing the resistance area product (RA) of the tunnel barrier. Finally, we link our single device reliability studies to similar endurance studies performed on our fully functional chips.

Perpendicular magnetic anisotropy (PMA) ferromagnetic CoFeB with dual MgO interfaces is an attractive material system for realizing magnetic memory applications that require highly efficient, high speed current-induced magnetic switching. Using this structure, a sub-nanometer CoFeB layer has the potential to simultaneously exhibit efficient, high speed switching in accordance with the conservation of spin angular momentum, and high thermal stability owing to the enhanced interfacial PMA that arises from the two CoFeB-MgO interfaces. However, the difficulty in attaining PMA in ultrathin CoFeB layers has imposed the use of thicker CoFeB layers which are incompatible with high speed requirements. In this work, we succeeded in depositing a functional CoFeB layer as thin as five monolayers between two MgO interfaces using magnetron sputtering. Remarkably, the insertion of Mg within the CoFeB gave rise to an ultrathin CoFeB layer with large anisotropy, high saturation magnetization, and good annealing stability to temperatures upwards of 400 °C. When combined with a low resistance-area product MgO tunnel barrier, ultrathin CoFeB magnetic tunnel junctions (MTJs) demonstrate switching voltages below 500 mV at speeds as fast as 1 ns in 30 nm devices, thus opening a new realm of high speed and highly efficient nonvolatile memory applications.

We present for the first time STT-MRAM devices with ultra low operating voltage and power compatible with next generation 0x node logic voltages. By engineering the tunnel barrier and improving the efficiency of the devices we report a record low writing voltage of 0.17V for a 1ppm error rate, which has been achieved for a 20ns write operation using a writing current of only 35uA. We further demonstrate error rates below 10 -9 at voltage and current at 0.25V and 50uA using 10ns writing pulses on the same 30nm devices with extended 400C thermal budget while preserving functionality confirm the almost unlimited endurance of these data and retention at 85°C. Finally, TDDB studies confirm the almost unlimited endurance of these devices at the operating voltage.

Luc THOMAS, Guenole JAN, Son LE, Santiago SERRANO-GUISAN, Yuan-Jen LEE, Huanlong LIU, Jian ZHU, Jodi IWATA-HARMS, Ru-Ying TONG, Sahil PATEL, Vignesh SUNDAR, Dongna SHEN, Yi YANG, Renren HE, Jesmin HAQ, Zhongjian TENG, Vinh LAM, Paul LIU, Hideaki FUKUZAWA, Yu-Jen WANG, Tom ZHONG, and Po-Kang WANG TDKHeadway Technologies, Inc., 463 S. Milpitas Bo ulevard, Milpitas CA 95035, USA, luc.thomas@headway.com

Spin-transfer-torque magnetic random access memory (STT-MRAM) is the most promising emerging non-volatile embedded memory. For most applications, a wide range of operating temperatures is required, for example −40 °C to +150 °C for automotive applications. This presents a challenge for STT-MRAM, because the magnetic anisotropy responsible for data retention decreases rapidly with temperature. In order to compensate for the loss of thermal stability at high temperature, the anisotropy of the devices must be increased. This in turn leads to larger write currents at lower temperatures, thus reducing the efficiency of the memory. Despite the importance of high-temperature performance of STT-MRAM for energy efficient design, thorough physical understanding of the key parameters driving its behavior is still lacking. Here we report on CoFeB free layers diluted with state-of-the-art non-magnetic metallic impurities. By varying the impurity material and concentration to modulate the magnetization, we demonstrate that the magnetization is the primary factor driving the temperature dependence of the anisotropy and thermal stability. We use this understanding to develop a simple model allowing for the prediction of thermal stability of STT-MRAM devices from blanket film properties, and find good agreement with direct measurements of patterned devices.

Last-Level-Cache applications at 0X technology nodes require devices switching reliably in less than 10ns at currents smaller than 50uA, while preserving data retention up to 85°C. In this paper, we show that both low Gilbert damping and low magnetic moment are the primary factors for efficient writing at nanosecond time scales. We report comprehensive device-level measurements of damping using both conventional free layer designs and an optimized free layer that combines low damping and low moment and meets LLC requirements.

Drug interactions with vitamine K antagonists (VKA) are expected. In France, Proton Pump Inhibitors (PPI) are widely prescribed and are often used as long-term treatments which raised concerns about long-term adverse effects and drug interactions. Well-known drug interactions with PPI are related to increase in gastric pH leading to VKA overdose. Recently, we were questioned about the possible etiology for low INR in a patient treated with fluindione and esomeprazole. A case of esomeprazole induced resistance to fluindione was already published and hepatic induction by PPI was considered to be implicated (1). We aimed to investigate about possible interactions between PPI and VKA, leading to lack of VKA efficacy.

Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) are based on Magnetic Tunnel Junctions (MTJs) made out of two ferromagnetic electrodes separated by a MgO tunnel barrier. Here we report experimental data of the STT-induced dynamics of a SAF RL in perpendicularly magnetized STT-MRAM devices. We show evidence of different RL dynamical modes depending on the SAF properties. We also develop an analytical model based on a 3-layer macrospin model, which allows us to reproduce the main feature of the experimental data and to derive a phase diagram of the RL dynamics. Experimental data of RL dynamics are obtained using time-resolved resistance measurements of individual MRAM devices.

Scaling STT-MRAM cells beyond 1X technology nodes will require MTJ devices smaller than 30 nm. For such small sizes, process-induced damage becomes a primary factor of device performance. A robust method of assessing magnetic properties of sub-30 nm devices is thus needed. Here we report measurements of the anisotropy field H K down to 20 nm devices using ST-FMR. We show that H K increases for decreasing sizes. The interfacial anisotropy field exceeds 23 kOe, leading to Hk larger than 13 kOe for 20 nm devices under optimal process conditions. Using insight from micromagnetic simulations, we develop a simple model to fit Hk size dependence, allowing us to quantify magnetic edge damage for various process conditions.

External magnetic field resistance under write, read operations for perpendicular STT-MRAM qualified for 260°C solder reflow is comprehensively reported for the first time. We show that the most critical polarization direction is writing from parallel to anti-parallel state with external field opposed to both the final free layer direction and the bottom pinned layer direction. It is also found that free layer failure to switch is the major cause rather than unexpected pinned layer flipping. Furthermore, various key factors including temperature, write condition and MTJ film stack are also studied here. Finally, we demonstrate that a low chip failure rate of 0.001 ppm can be achieved with an ECC scheme for external magnetic fields up to 240 Oe at 85°C.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is the leading technology for next generation non-volatile embedded memories. In this presentation, we use Spin-Torque Ferromagnetic Resonance (ST-FMR) to measure the anisotropy field of perpendicularly magnetized devices down to 25 nm in size. We show that the effective anisotropy field HK eff , including the demagnetizing field, exceeds 10 kOe at room temperature. The corresponding interfacial anisotropy field is close to 20 kOe. The magnetic tunnel junction (MTJ) stack used in this work consists of perpendicularly magnetized CoFeB-based magnetic electrodes separated by a MgO tunnel barrier. The reference layer (RL) is made out of a synthetic antiferromagnet (SAF) so as to minimize the dipolar field on the free layer (FL).

We report the current-induced domain-wall (CIDW) motion along the electron flow in the perpendicularly magnetized Co/Ni/Co structure sandwiched between the top and bottom Pt layers, observed by means of the Kerr microscope. As the lower Co thickness increases, the DW velocity for the electron flow is significantly increased, and also its motion becomes more stable irrespective of various current pulses. From the longitudinal field dependence of the DW velocity, it is found that the increase of the lower Co thickness increases a Dyzaloshinskii-Moriya interaction in the bottom Co/Pt interface, which results in the increase of the chiral spin torque, responsible for the increase of the DW velocity along the electron flow.

Significant progresses have been made in recent years in perpendicular spin torque transfer magnetic random access memory (pSTT-MRAM) technology development by many companies or organizations. Commercialization of pSTT-MRAM is more real today than ever in the long history of MRAM technology development. We have recently reported fully functional pSTT-MRAM chips and macros with sub-5ns writing speed based on 90nm and 40nm node CMOS technologies [1,2]. These technologies can be potentially used to replace current embedded non-volatile memories such as embedded flash memories or SRAM and be applies to energy efficient applications such as internet of thing (IOT). In this presentation, we will review recent progresses and discuss STT-MRAM scaling challenges for product at 28nm technology node and beyond in terms of integration schemes as well as magnetic and electrical transport properties. We will also discuss the potential solutions that we see for these challenges. References: [1] G. Jan, Symp VLSI Tech, 2014. pp 50-51. [2] Yu Lu et al, IDEM Technical Digest, 2015 (in press)

We have studied the current-induced domain wall (CIDW) dynamics in perpendicularly magnetized Co/Ni multilayers deposited on Au underlayer, where the conventional spin transfer torque governs the domain wall dynamics, by the Kerr microscope. It is found that the DW angle tilting following Oersted field profile plays an important role in domain wall (DW) motion at high current density J by decreasing DW velocity with the increasing J, while distorting its DW morphology. Also we find that the DW pinning becomes pronounced as the anisotropy decreases by increasing number of Co/Ni repeats. Most remarkably, the DW tilting angle changes its sign by inserting ultrathin Pt layer between Au and Co layer, which suggests that the Dzyaloshinskii–Moriya interaction and spin Hall effect induces opposite effect in DW tilting. Our findings can be of use for application of CIDW to spintronics with perpendicularly magnetized systems.

We present recent advances in writing speed of pSTT_MRAM which demonstrate its potential as a candidate for replacement of LCC cache for advanced technology nodes as well as applications where non-volatility may be needed. In this paper we explore the feasibility of sub-ns switching of devices and their characterization using comprehensive time resolved electrical measurement of the reversal mechanism. We show that the switching mechanism can be described as a simple nucleation followed by propagation model that can be characterized statistically. We further demonstrate that after optimization of the Magnetic Tunnel Junction (MTJ) stack, single devices can be switched reliably using write pulse length down to 750ps while preserving functionality and data retention @ 125°C. Results of the integration at array level on an 8MB test vehicle are also presented allowing full array writing using 3ns pulses without ECC and demonstrated data retention of 10 years (1ppm) at 125°C.

A comprehensive reliability analysis of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (pSTT-MRAM) is demonstrated that pSTT-MRAM is capable of fast write, more than 107 cycles endurance, less than 10 -20 read disturb error rate at 125°C, and 10 years data retention up to 225°C at chip level. Furthermore, we prove for the first time that pSTT-MRAM technology can withstand reflow soldering at 260°C, thus enabling the opportunity for embedded nonvolatile memories in consumer and automotive Microcontrollers (MCUs) applications.

STT-MRAM technology has been attracting renewed attention since the embedability of a working STT-MRAM design has been demonstrated [1]. In this paper we expand on the versatility of STT-MRAM by demonstrating the conversion of a standard STT-MRAM cell to a One Time Programmable (OTP) anti-fuse cell. Both designs are integrated at the Mbit level on a single chip using the same magnetic stack, processing and CMOS cell design. A single BEOL mask change can convert an STT-MRAM device to an OTP design by simply reducing its size. The increased resistance yields larger voltage drop across the device, due to the voltage divider effect in the 1T-1MTJ cell and is sufficient to trigger reliable dielectric breakdown of the oxide tunnel barrier, effectively shorting the device. In this paper we demonstrate the seamless integration of an OTP based on STT-MRAM and 100% programming and reading yield at the Mbit level.

We demonstrate a highly efficient and simple scheme for injecting domain walls into magnetic nanowires. The spin transfer torque from nanosecond long, unipolar, current pulses that cross a 90° magnetization boundary together with the fringing magnetic fields inherently prevalent at the boundary, allow for the injection of single or a continual stream of domain walls. Remarkably, the currents needed for this "in-line" domain wall injection scheme are at least one hundred times smaller than conventional methods.