The interconnected Mesh Power System (IMPS) is an interconnect topology that combines power distribution and signal wiring on a set of X-running and Y-running metal layers. In simplest form, a complete interconnect structure can be built with only two layers of metal. This paper compares an IMPS implementation in four metal layers with the conventional four layer buried stripline (power, X signal, Y signal, ground.) The signal routing density is the same for both configurations. Test vehicles M,ere built in high temperature cofired ceramic, and populated with active CMOS driver chips to allow measurements of signal line crosstalk and power distribution noise. Structures for measuring line characteristics were included.This paper will describe the design and construction of the test vehicles, and will derail the measurement results. The utility of the (MPS topology for high-speed digital signals is indicated by the reduction in signal crosstalk by a factor of two to three, combined with a modest reduction in power distribution noise. Distributed substrate decoupling capacitance was a factor of four better in IMPS than in buried stripline. Uniform 50-ohm transmission lines were fabricated in both topologies and their performance confirmed by TDR measurements.A real microprocessor package using IMPS was also designed, constructed, and evaluated. Whereas the original package required seven ceramic layers, IMPS allowed the package to be reduced to five layers. Both packages were essentially equivalent in performance metrics, but again the (MPS version reduced crosstalk by a factor of two. These data will also be presented.

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long line becomes highly resistive resulting in unacceptable delays. One possible solution to the problem is to transfer these lines off-chip using a Seamless High Off-Chip Connectivity (SHOCC) packaging concept, including dense chip input/output (I/O) interconnects to an interposing high density substrate. By replacing the thin, narrow aluminum (AZ)/copper (Cu) or Al on-chip interconnect lines with thicker, wider, and less resistive Cu, integrated circuit (IC) performance can be improved. By using area array and MCM-D technology to flip chips onto a high-density laminate, a seamless connection between the chips can be achieved. A high-density MCM-D/L process has been developed for the SHOCC technology where a double-sided, laminated board with 12-mil through-holes and patterned copper ball-grid-array/catch pads were used as the starting substrate.

The development of thin film capacitors embedded in flexible polyimide is attractive to the electronics packaging industry. In fact, thin film capacitors on flexible substrates have the potential for extensive use in high frequency applications (>500 MHz). Consequently, the precise characterization of such devices is extremely important. The ability to miniaturize capacitors and to fabricate them as part of the package is achieved by using dielectrics with high dielectric constants, such as tantalum oxide. This paper reports on the design, fabrication, electrical characterization, reliability testing, and dielectric surface evaluation of tantalum oxide capacitors embedded in 50 mu m thick polyimide substrates.

Today's electronics demand that systems to be capable of operating at high speeds, handle high power levels, be lightweight, and be cost effective. An attractive choice for meeting these requirements is the 3-D multichip module (MCM) approach, although it presents challenges in terms of thermal management, reliable high density electrical interconnects, and mechanical configuration. This paper addresses the thermal and electrical aspects of flexible substrate (or flex) 3-D MCM structures. A 3-D configuration using a polymer-based flex substrate has been attempted, and modeling results of this work have shown the feasibility of the concept. Experimental results are presented and discussed in terms of their deviations from the modeling results. The flex configuration is discussed in terms of the high density electrical interconnection using elastomers and surface mount connections between flex layers. Although flex has a low thermal conductivity tests and simulations have shown that as much as 6 watts can be dissipated through a dmm x 6mm area. Vias in the flex contribute to an increased interconnect density and would also assist with thermal management. Moreover, epoxy used to attach die to the flex and the flex to the heat spreader should be used sparingly, to reduce thermal resistance. Significantly better thermal and electrical performance can be realized using a flip chip connection configuration versus wire bonded chips, since a flipped die is best cooled from the upper side. In this case, consideration must be given to stresses involved in the assembly process and as a result of operation. The implications of such factors on the performance of the electronic system are discussed. Furthermore, the impact of the use of embedded passives on interconnect and passive device densities in terms of electrical performance is addressed. Finally, the future direction of the work is reviewed.

One of the many possible applications of high-temperature superconducting (HTS) thin films is as interconnect in a hybrid multichip module (MCM). Such a module would consist of a substrate containing superconducting interconnect and conventional CMOS circuitry chips. Since HTS thin films are crystalline in nature and deposited at high temperatures, many difficulties arise in the formation of epitaxial multi-layer superconducting structures. The Flip-Mesh Superconducting MCM provides an alternative to a multi-layer substrate by interfacing multiple single-layer substrates, thereby reducing the epitaxy requirement to one layer per substrate. This substrate interfacing is accomplished by forming X-plane interconnect on one substrate and Y-plane interconnect on another, and connecting them using I/O technology. The reduced epitaxy requirement of Flip-Mesh also makes the implementation of amorphous substrates more feasible. The Interconnected Mesh Power System (IMPS) topology used so that power, ground, and signals can be fabricated on two planes.

A process for fabricating high temperature superconducting (HTS) multichip module - deposited (MCM-D) substrates has been developed and tested. The module consists of two digital gallium arsenide bare die connected by YBa2Cu3O7-delta (YBCO) HTS interconnects to form two ring oscillators on a 2.25 cm(2) MCM-D substrate. The interconnections consist of two wiring layers of YBCO separated by a 4-5 mu m silicon dioxide interlevel dielectric. The 50 mu m wide signal lines are routed between 150 mu m power and ground lines with 75 mu m spacings to form an interconnected mesh power system (IMPS). Connection between the two YBCO layers is accomplished with low contact resistance 40 mu m gold vias through the interlevel dielectric layer. Ultrasonic Al wire bonds serve as electrical connections to gold/YBCO bond pads on the MCM substrate.

A design implementation package for the automation of advanced IMP MCM topologies has been developed. The IMPS topology is a patented development of the University of Arkansas which allows a complete MCM with low impedance power distribution and dense signal interconnect, to be built on only two metal layers. The IMPS topology consists of a large number of interwoven power distribution lines. The large volume of layout structures in the IMPS topology, requires the assistance of a computer-aided design package. This paper describes advanced IMPS topologies and how the IMPS design package, along with Mentor Graphics MCM Design Station, implement the different types of meshes. An example design is used to illustrate the use of the methodology. The advanced IMPS topologies described include the nonuniform IMPS mesh, which allows for higher signal interconnect density at congested locations; the partitioned IMPS mesh, which allows for different mesh structures at different locations in the same design and the asymmetric IMPS mesh, which allows for variations in power supply impedances

A new MCM design topology, the interconnected Mesh Power System (IMPS), which reduces the conventional four layer MCM to a two layer structure is presented. The characterization of power distribution and signal transmission properties of IMPS are discussed