An array of miniaturized cylindrical quadrupole ion traps, with a radius of 20 microm, is fabricated using silicon micromachining using phosphorus doped polysilicon and silicon dioxide for the purpose of creating a mass spectrometer on a chip. We have operated the array for mass-selective ion ejection and mass analysis using Xe ions at a pressure of 10(-4). The scaling rules for the ion trap in relation to operating pressure, voltage, and frequency are examined.

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.

This paper describes the design and performance of a 64-channel equalization and blocking filter. It utilizes a free space lens and grating multiplexer with micromechanical tilt mirrors providing variable attenuation. The module achieves a 5-dB insertion loss with a 3-dB passband of 87 GHz for 100-GHz spaced channels. The attenuation range achieved is in excess of 35 dB, making it suitable for wavelength blocking in switching applications. The device has been demonstrated to be compatible with 10- and 40-Gb/s transmission.

Recently, optical MEMS devices have gained considerable attention in the telecommunications industry-particularly in the optical networking and switching arenas. Since optical MEMS are micro-systems which rely on high precision optics, electronics and mechanics working in close concert, these emerging devices pose some unique packaging challenges yet to be addressed by the general packaging industry. Optical MEMS packages often are required to provide both optical and electrical access, hermeticity, mechanical strength, dimensional stability and long-term reliability. Hermetic optical access necessitates the use of metallized and anti-reflection coated windows, and ever-increasing electrical I/O count has prompted the use of higher density substrate/package technologies. Taking these requirements into consideration, we explore three ceramic packaging technologies, namely High Temperature Co-fired Ceramic (HTCC), Low Temperature Co-fired Ceramic (LTCC) and thin-film ceramic technologies. In this paper, we describe some optical MEMS packages designed using these three technologies and discuss their substrate designs, package materials, ease of integration and assembly.

Describes a 64 x 64 beam steering optical cross connect constructed using surface micromachined mirrors. It used a curved mirror as a Fourier transform element and to fold the optical system. Both micromechanical switches mirror arrays are fabricated on a single chip and packaged in a single package. The switch fabric size, at 100×120×20 mm, is compatible with mounting on a standard circuit card. ...

Due to its enormous bandwidth, optical fiber has become the medium of choice for the high-speed, distant transmission of voice and data. Thus, a large portion of a modern telecommunications network is optical in nature. A single fiber might carry light at a single wavelength-modulated at rates of 2.5, 10, or even 40 Gbit/s-for hundreds of kilometers without regeneration. Alternatively, a single fiber might carry dozens of independent optical signals, all at slightly different wavelengths-so-called Dense Wavelength Division Multiplexing (DWDM).Historically, any manipulation of such optical data streams first required conversion to the electrical domain. Here, signals could be switched, added, dropped or re-shaped as needed, and then re-converted to their optical counterparts. But such optical-to-electrical and electrical-to-optical conversions require expensive hardware and can create a bandwidth bottleneck if the electronics become the limiting factor.Recently, MEMS (Micro-Electro-Mechanical-Systems) devices have become key elements in real components and subsystems used for construction of state-of-the-art DWDM optical networks. Here, tiny bits of sculpted silicon interact directly with the optical signals. Microscopic mirrors can switch light from one fiber to another. Other simple structures can be used to add, drop, or attenuate individual wavelengths at will. All while signals remain in the optical domain.With such novel devices come some novel packaging challenges. In our AEMS packaging efforts to date, we have generally resorted to ceramic structures to provide hermeticity and mechanical stability. Windows have been incorporated to allow interaction of light and MEMS devices. And electrical I/O counts have ranged from dozens for simple applications, to thousands for large optical cross-connect mirror arrays. In this work, we'll provide a sampling of such MEMS packaging projects, and the rationale behind our design decisions.

We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.

Micro-optoelectromechanical systems (MOEMS) having valuable performance, size, and cost attributes offer novel solutions to the design of lightwave network elements. We will discuss the new challenges that realizing these benefits presents to the field of photonic packaging.

Chip-on-chip technology is a low-cost alternate solution to embedded memory technology for achieving tight logic and memory integration. However, with the inclusion of two or more bare dies in a common package, we inevitably alter the electrical characteristics of these integrated circuit (IC) devices. To ensure each device functions as designed, we identify several key electrical issues associated with signal transmission, power distribution system, and input/output (I/O) buffers that could potentially limit the performance of chip-on-chip modules. In addition, we provide a detailed comparison between chip-on-chip and conventional printed wiring board (PWB) implementations to demonstrate the superior electrical characteristics of these chip-on-chip modules.

We show an example design of a cellular telephone that demonstrates the marked contrast between passive component usage in its base-band and radio sections. We discuss the performance demands that applications like these place on passive components and how these demands relate to the technology used to build the components. Recently, we have demonstrated and reported on the use of silicon-on-silicon thin film modules to integrate the tank resonator circuit of the 1 GHz UHF VCO in a GSM transceiver. We discuss some of the ways that these results can be extended to take further advantage of component integration. A unique characteristic of modules used in RF applications is the integration of thin-film spiral inductors. One of the concerns in the tight integration of these components is crosstalk arising from mutual inductive coupling between components. We have calculated the mutual inductive coupling between spiral inductors, with and without ground planes, and present representative examples from typical module designs

We recently described a flip-chip package with integrated thin-film inductors and capacitors in a VCO tank circuit of a single-chip GSM transceiver IC. By embedding the passive components in a Si-on-Si substrate, we eliminated spurious resonances that were caused by the parasitics of the original 64-TQFP IC package. However, compared with the bare die, the resultant Si-on-Si structure is larger in all dimensions due to the inclusion of a flip-chip mounted transceiver IC and a surface-mount varactor. We have developed a novel BGA package structure with a hole milled in the center to accommodate the silicon-on-silicon assembly. The interconnections rely exclusively on flip-chip solder technology and no wire-bonds are needed. To verify that the package does not degrade the performance of the RF circuits, we have performed electromagnetic field simulations to extract critical inductance and capacitance parameters. Parasitic inductances of the original TQFP and the new packages are comparable due to their similar dimensions. Nonetheless, a major advantage of the new package structure is that it permits the integration of key passive components inside the package where they are unaffected by package parasitic impedances.

Chip-on-chip MCM packaging combines the benefits of conventional MCM methods with conventional ASIC/commercial memory printed circuit board design methods. COC can reduce board space, increase performance, maintain a cost competitive position and offer an alternative to embedded SRAM and DRAM in the appropriate situations. We show that additional testing for known-good-die is minimal, functional to parametric memory yield is very high, COC module assembly is simple and straightforward, and final packaging is essentially identical to conventional ASIC packaging processes

We report an integrated VCO in a GSM transceiver with less than 1% frequency error in the first design and spurious-free frequency response. The first-design success with high accuracy is due to considering the package as part of the circuit design and included in optimization. The spurious-free frequency response is achieved by carefully designing a high-Q (37.5 at 1 GHz) inductor and a co-planar stripline in the VCO resonator.

We have analyzed the power distribution system and signal integrity of a silicon-on-silicon multichip module designed for asynchronous transfer mode (ATM) switching applications. The module contains four AT&T T7650 Phoenix 8-bit parallel buffered 2x2 switching node ICs configured into a 4x4 node with an operating frequency of 40 MHz. We compared the signal integrity of the design based on our MCM technology with that of typical PWB technologies The results indicate that crosstalk and ringing are greatly reduced in MCM-based designs. We also investigated the effectiveness of decoupling capacitors on simultaneous switching noise, comparing the performance of ring- and plane-type power distribution systems. For this example, rye find little difference between the two for signal rise times greater than 2 ns.

A new low-cost multichip module (MCM) topology, the interconnected mesh power system (IMPS), has been shown capable of reducing the metal layers of a conventional four-layer MCM by half. To provide a complete MCM on only two metal layers, the IMPS topology provides a unique and complex power distribution system and signal transmission environment. This paper reports on models of the IMPS structure based on finite-difference/partial-inductance methods and PSpice simulation. The models can easily he constructed using a commercial three-dimensional (3-D) field solver and the circuit models can be solved by PSpice. The agreement between the modeled and measured results is excellent. Discrepancies between models and results are also discussed.

We have designed multichip modules using three alternative technologies for a variety of applications, and have used the results to study the impact of miniaturization and passive component integration on module size, distribution of net length and estimated cost. We have chosen representative applications that include: a digital application with dense interconnections, a mixed-signal application for low-end portable electronics and an analog application requiring a large number of passive components. We compare conventional, laminate-based MCM technology with advanced thin-film-on-laminate technology and silicon-based thin-film MCM technology. We find that the advanced, highly miniaturized technologies result not only in higher packaging density and shorter average net length, but in lower estimated module cost as well. Passive component integration can also lower module cost especially in mixed-signal and analog applications.