In this paper, we present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) project. Faust is based on the open-source multi-format floating-point ar-chitecture FPnew that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the most recent IEEE 754-2019 FP standard. Faust is extensively tested, mature and configurable, enabling ease of integration, as will be demonstrated in the paper. Faust can produce two binary32 operations or one binary64 operation per clock cycle. We have also developed FPU-V, an update of the SoftFloat-based reference model as a critical part of the UVM-based universal and extensible FPU verification environment. Faust was integrated and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the first EPI Accelerator Test Chip in GlobalFoundries 22FDX technology, and was shown fully operational at a target frequency of 1 GHz.

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

In this paper is presented an area efficient reusable architecture for integer one dimensional Discrete Cosine Transform (1D DCT) with adjustable transform sizes in High Efficiency Video Coding (HEVC). Optimization is based on exploiting of symmetry and subset properties of the transform matrix. The proposed multiply-accumulate architecture is fully pipelined and applicable for all transform sizes. It provides the interface over which the processing system can control the datapath of the transform process and the synchronization channel that enables the system to receive the feedback information about utilization from the device. An intuitive line approach for calculating transform coefficients for all transform sizes was used instead of the commonly applied recursive decomposition approach. This approach simplifies disabling of lines that are not employed for a particular transform size. The proposed architecture is implemented on the FPGA platform, can operate at 407,5 MHz, achieves throughput of 815 Msps and can support encoding of a 4K UHD@30 fps video sequence in real time.

Continuous growth of video traffic and video services, especially in the field of high resolution and high-quality video content, places heavy demands on video coding and its implementations. High Efficiency Video Coding (HEVC) standard doubles the compression efficiency of its predecessor H.264/AVC at the cost of high computational complexity. To address those computing issues high-performance video processing takes advantage of heterogeneous multiprocessor platforms. In this paper, we present a highly performance-optimized HEVC transform and quantization kernel with all-zero-block (ALB) identification designed for execution on a Graphics Processor Unit (GPU). Performance optimization strategy involved all three aspects of parallel design, exposing as much of the application's intrinsic parallelism as possible, exploitation of high throughput memory and efficient instruction usage. It combines efficient mapping of transform blocks to thread-blocks and efficient vectorized access patterns to shared memory for all transform sizes supported in the standard. Two different GPUs of the same architecture were used to evaluate proposed implementation. Achieved processing times are 6.03 and 23.94 ms for DCI 4K and 8K Full Format, respectively. Speedup factors compared to CPU, cuBLAS and AVX2 implementations are up to 80, 19 and 4 times respectively. Proposed implementation outperforms previous work 1.22 times.

When analysing Internet traffic today it can be found that digital video content prevails. Its domination will continue to grow in the upcoming years and reach 82% of all traffic by 2021. If converted to Internet video minutes per second, this equals about one million video minutes per second. Providing and supporting improved compression capability is therefore expected from video processing devices. This will relieve the pressure on storage systems and communication networks while creating preconditions for further development of video services. Transform and quantization is one of the most compute-intensive parts of modern hybrid video coding systems where coding algorithm itself is commonly standardized. High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard which achieves high compression efficiency at the cost of high computational complexity. In this paper we present highly parallel GPU accelerator for HEVC transform and quantization which targets most common heterogeneous computing CPU+GPU system. The accelerator is implemented using CUDA programming model. All the relevant state-of-the-art techniques related to kernel vectorization, shared memory optimization and overlapping data transfers with computation were investigated, customized and carefully combined to obtain a performance efficient solution across all applicable transform sizes. The proposed solution is compared against reference implementation which uses NVIDIA cuBLAS library to perform the same work. Obtained speedup factors for DCI 4K frame are 2.46 times for largest transform size and 130.17 times for smallest transform size what revealed substantial performance gap of this library when targeting GPU of the Kepler architecture. Achieved processing time of frame transform and quantization are up to 4.82 ms.

This paper presents Bolt65 HEVC software/hardware suite, consisting of encoder, decoder and transcoder, that is being developed at Faculty of electrical engineering and computing, University of Zagreb. One of the primary focus of Bolt65 is achieving Just-in-Time requirements that would enable video encoding/transcoding on demand. To achieve this goal, Bolt65 tries to maximally utilize all software and hardware components of the system on different architectures, from homogeneous CPU architectures with vector extensions to heterogeneous, accelerator-based architectures that have different types of processing cores. CPU-only implementation of Bolt65 was compared with referent HM HEVC software in three different encoding configurations: All Intra (AI), Low delay (LD) and Random Access (RA). Results show that Bolt65 achieves significant speed-up in all configurations and bitrate savings in AI and RA modes while sacrificing quality in order to achieve just-in-time requirements.

Video encoding based on novel HEVC standard is an extremely computationally expensive process and achieving efficient encoding requires intelligent utilization of all available resources, from both software and hardware perspective. Profiling and analysis of the encoding process identified Discrete cosine transform (DCT) as one of the key kernels that consume most of the time in the application's runtime. Therefore, high-throughput, fully-pipelined hardware accelerator was designed in FPGA and integrated into MANGO platform. MANGO platform is heterogeneous H PC system that consists of different types of nodes, from general purpose nodes (GN) to heterogeneous nodes (HN). While executing specific kernels on GN nodes is a straightforward process, executing kernels on accelerator-based HNs is a more complex procedure and requires specific integration to successfully exploit heterogeneous architecture. This paper presents performance-efficient integration of DCT hardware accelerator in MANGO platform, focusing on the performance of the encoder while maintaining coding efficiency and video quality of the encoded bitstream. Several approaches were considered, tested and compared; from the standalone integration where series of single tasks were offloaded to the DCT accelerator, to more complex solutions based on smart buffer utilization.

This paper proposes a novel algorithm for dynamic tile partitioning to achieve the optimal workload balance for parallel processing architectures in just-in-time HEVC encoding. Tile boundaries are dynamically shifted depending on the tile cost, a value that denotes predicted computational complexity of a single tile in a frame. The overall cost of a tile is determined as a combination of costs of three computationally most expensive and resource-hungry operations in HEVC encoding: prediction, transformation, and entropy coding. The algorithm aims at exploiting different types of processing architectures, from homogeneous multicore CPU architectures to heterogeneous architectures in the actual conditions in which streaming servers operate. The experimental results show that the proposed algorithm outperforms uniform tiling, by up to 5.5% in processing time, while maintaining the same video quality and bitrate. Compared to the state-of-the-art algorithms, the proposed algorithm achieves up to 8.85% speedup depending on the number of videos that are being encoded concurrently on a video streaming server.

The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated.

Next-generation High-Performance Computing (HPC) applications need to tackle outstanding computational complexity while meeting latency and Quality-of-Service constraints. Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the flexibility to meet the requirements of next-generation HPC. However, heterogeneity brings new challenges to efficient chip thermal management. In this context, accurate and fast thermal simulators are becoming crucial to understand and exploit the trade-offs brought by heterogeneous MPSoCs. In this paper, we first thermally characterize a next-generation HPC workload, the online video transcoding application, using a highly-accurate Infra-Red (IR) microscope. Second, we extend the 3D-ICE thermal simulation tool with a new generic heat spreader model capable of accurately reproducing package surface temperature, with an average error of 6.8% for the hot spots of the chip. Our model is used to characterize the thermal behaviour of the online transcoding application when running on a heterogeneous MPSoC. Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms.

In this paper we present the novel platform for accessing multimedia e-health content adapted for elders. ICT solutions offered on market today are not adapted to elder people. Home Health Smart TV was developed in order to solve this issue. Integration with social network features, like video communication and personalized calendar, solves another concern for elder population social isolation. Elder population is accustomed to TV devices and with this specially designed platform they can access their medical data and communicate with friends, family or medical staff in a simple way that doesn’t require computer literacy.

Turkey has created an e-health vision along with the Health Transformation Program. In this framework, standard coding systems such as standard definitions of the institutions, databank of healthcare providers, standard disease, drug and medical supplies classifications have been developed and a national clinical data warehouse (Health-NET) was established. Health-NET is an integrated, safe, fast and expandable health information system which aims to improve efficiency and quality of health services by collecting all kinds of data produced in the health institutions in line with the standards and generating information adequate for all stakeholders of the collected data.

In this paper we present the novel platform for accessing multimedia e-health content adapted for elders. Health market is filled with different ICT solutions which provide access to the patient's healthcare records through patient portals. The problem is that none of them are adapted to elder population. Home Health Smart TV platform was developed in order to solve this issue. Elder population is accustomed to TV devices and with this specially designed platform they can access their medical data in a simple way that does not require computer literacy.

The paper describes telecare procedure concerning patients aged between 65-85 years with at least 2 chronic diseases including hypertension (ICD I10), diabetes (ICD E 11), chronic obstructive pulmonary disease (ICD J44) or heart failure (ICD J50). Ultimately, the project will involve 100 patients qualified on the basis of medical history (last stay in hospital) divided in two groups. In the qualified group, each patient must have at least 60 points according to the Barthl scale. The first group comprises 50 patients taken care of by tele monitoring, which was provided to them with measuring equipment to be able to assess the selected parameters at home (depending on the chronic disease). Then, the results are transmitted automatically via mobile phone network to LSV Telecare (Lower Silesia Voivodeship Telecare) system. The other group of patients consists of those, who were not included in the home monitoring. They are provided with medical care within the current Polish health care system. In this paper we present scenarios and models of business processes, necessary to achieve the objectives of the Care Well project, which is implemented under Competitiveness and Innovation Framework Programme 2007-2013 (project "Multi-Level Integration for Patients with Complex Needs"; grant agreement no: 620983) . The project involves 13 partners from 8 EU countries project duration is 36 months. The technical parts of the project include tests and examinations of the economic and social effects, as well as indicators of the quality of life based on ICT platform for communication and exchange of medical data, that are essential in the treatment of patients qualified for

Most approaches for modelling processes neglect the high degree of distributed decision making in the hospital domain where processes are coordinated by local authorities. The paradigm of fractal organizations combined with the decentralized characteristics of distributed Artificial Intelligence may help to understand and model the problem. This paper presents ongoing research and contributes a meta-model for modelling processes in hospitals with multiagent systems as fractals of a logistics supply network and incorporates data analytics methods to identify dependencies between different fractals. The presented approach is evaluated by analyzing a hospital scenario involving multiple fractals in a patient-centric process.

Integrated care that starts with patients taking care for their health, that includes truly multidisciplinary team approach to treating patients’ conditions and that utilizes enormous existing common knowledge in an efficient way, is one big step towards increasing healthcare provisioning quality while in the same time having healthcare cost under control. The foundation of the integrated care is timely availability of comprehensive information for all stakeholders within healthcare processes independent on their location and information system or application they use. The absolute precondition for this is ability of different IT systems / applications to exchange and display information in a way that is not only comprehensible to all stakeholders but also means the same to all of them. This ability is called interoperability. In this paper, overview of different interoperability aspects for electronic healthcare records / personal healthcare records is given. The main standards / initiatives are explained along with some challenges and possible way forward. Index Terms — Electronic Healthcare Record, Personal Healthcare Record, interoperability EN 13606, openEHR, archetype, HL7 CDA, IHE