Superblocks are widely used in SSDs to exploit internal parallelism thus improving I/O throughput. Although dynamic-size superblock schemes enhance space utilization for varied workloads, they introduce internal fragmentation and impact overall performance. To address this issue, we propose Buddy , a novel dynamic-size superblock management scheme based on the buddy system, which adapts to I/O patterns by dynamically splitting and merging superblocks. This approach maintains large blocks to preserve parallelism for sequential writes and generates smaller blocks on demand to handle random writes effectively. We further introduce the expansion GC mechanism to adaptively adjust GC unit size based on I/O intensity and GC efficiency for alleviating fragmentation and preserving SSD parallelism. Trace-driven evaluations with real-world benchmarks demonstrate that our approach can reduce average I/O latency and GC-induced data migration by 47.0 % and 24.5 %, respectively, compared to state-of-the-art superblock management techniques.
LSM-based key-value stores are widely used due to their write efficiency and scalability. However, their background compaction process requires substantial data movement between the host and storage devices, resulting in inefficient resource usage, frequent write stalls, and degraded overall throughput. Existing optimizations fail to address the performance bottlenecks caused by excessive system interconnect traffic. Although in-storage computing offers a promising way to mitigate data transfer overhead, prior works typically offload all compaction tasks blindly to computational storage devices. Our preliminary experiments show that such naive offloading leads to performance inefficiency due to CSD resource constraints. In this work, we propose CSD-CoKV + , a host-CSD collaborative framework that enables efficient compaction acceleration for LSM-based KV stores. Specifically, we design a semantic-aware offloader to selectively dispatch suitable compaction jobs to CSDs, together with a lightweight FPGA-based compaction kernel for efficient in-storage execution under constrained device resources. In addition, we develop a range-partitioned data organization with two-level load balancing to preserve locality and improve scalability across CSD arrays, and further introduce a host-device hierarchical cache to better exploit device-level locality in the read path. Evaluations on a real SmartSSD-based prototype show that, with the default host-only baseline, CSD-CoKV + improves write throughput by up to 2.26 × and boosts compaction throughput by up to 3.42 ×, while improving read throughput by up to 28.5%.
Machine learning models excel across applications like medical diagnostics, weather forecasting, natural language processing and autonomous driving, yet their inadequate handling of uncertainty remains crucial for safety-critical applications. Traditional neural networks fail to recognize out-of-domain (OOD) data, often producing incorrect predictions without indicating uncertainty. Bayesian neural networks (BNNs) offer a principled framework for uncertainty estimation by providing statistically grounded probabilities alongside predictions. Despite these advantages, BNNs suffer from high computational costs in both training and prediction. Predictions require sampling over weight distributions and multiple forward passes. To address this challenge, the Probabilistic Forward Pass (PFP) serves as an extreme approximation of Stochastic Variational Inference (SVI). While SVI assumes Gaussian-distributed weights without restrictions on activations, PFP extends this assumption to activations. This enables a fully analytical uncertainty propagation, replacing multiple forward passes with a single, more complex forward pass operating on probability distributions. Thus, PFP requires specialized Gaussian-propagating operators absent from standard deep learning libraries. We present an end-to-end pipeline for training, compilation, optimization, and deployment of PFP-based BNNs on embedded ARM CPUs. By implementing custom operators in the deep learning compiler TVM, we develop a dedicated operator library for multilayer perceptrons and convolutional neural networks. Multiple operator implementations, along with manual and automatic tuning techniques, are applied to maximize efficiency. Ablation studies show that PFP consistently outperforms SVI in computational efficiency. For small mini-batch sizes, critical for low-latency applications, our approach achieves speedups of up to 3900 ×. Our results show that PFP-based BNNs achieve performance comparable to SVI-BNNs for uncertainty disentanglement on the Dirty-MNIST dataset and for complex OOD detection on CIFAR-10 against SVHN, all while significantly reducing computational overhead. These findings underscore the potential of combining Bayesian approximations with code generation and operator tuning to accelerate BNN predictions and enable their efficient deployment on resource-constrained embedded systems.
As parallel codes are scaled to larger computing systems, performance models play a crucial role in identifying potential bottlenecks. However, constructing these models analytically is often challenging. Empirical models based on performance measurements provide a practical alternative, but measurements on high-performance computing (HPC) systems are frequently affected by noise, which can lead to misleading predictions. To mitigate the impact of noise, we introduce application-specific effort-based priors into the modeling process. These priors are derived from noise-resilient measurements of computational effort, combined with domain knowledge about common algorithms used in communication routines. By incorporating these priors, we effectively constrain the model’s search space, eliminating complexity classes that capture noise rather than true performance characteristics. This approach keeps the models closely aligned with theoretical expectations and substantially enhances their predictive accuracy. Moreover, it reduces experimental overhead by cutting the number of repeated measurements by half.
With the stagnation of single-threaded performance, the need for optimizations targeting sequential code performance is greater than ever before. Modern workloads have also been growing in code footprint, exposing a bottleneck in the processor front-end, specifically its inability to maintain a sufficiently high fetch throughput to saturate available execution units. To address them, two optimizations exist in modern processors: (1) Fetch-Directed Instruction Prefetching (FDIP) and (2) the micro-op cache ( μ op cache), both of which improve fetch throughput leading to improved overall performance. However, since they target the same code regions, in the presence of FDIP, the μ op cache becomes mostly redundant as a performance optimization. This work proposes JumpStart : a novel and lightweight mechanism that synergistically exploits hints from FDIP to early-detect a μ op cache miss and wake up the decode pipeline ahead of time, alleviating a key front-end bottleneck.
