The Maximum Common Subgraph (MCS) problem is a fundamental challenge in graph theory. It generalizes the subgraph isomorphism problem and is known to be NP-complete and difficult to approximate. This inherent complexity underscores the need for efficient solutions. This work introduces Hydra-MCS, a novel hybrid CPU-GPU approach that significantly accelerates MCS computation. Our method uses a lightweight metric to accurately estimate the remaining computation (RC) for a given solution. Then it uses this metric to offload computations to the GPU, maintain load balancing, and minimize unnecessary task sharing between threads. We identify the essential information the CPU and GPU must share to optimize performance by carefully analyzing our hybrid implementation. Furthermore, we discuss the substantial advantages of offloading computation to the GPU. Our method establishes a new state of the art in performance. Under matched CPU resources, GPU integration provides approximately a $3\times$ additional speedup over Hydra-MCS CPU and approximately a $4\times$ speedup over parallel McSplit on the scaling workload; across long-running benchmark instances, speedups over McSplit typically reach 4-$5\times$, with peaks exceeding $12\times$. We also address scalability and robustness, as our algorithm's behavior significantly surpasses that of the original as the number of threads increases and the problems become harder. A comprehensive analysis comparing solved instances over time demonstrates that the hybrid implementation consistently solves 30-40% of the instances not yet solved by the original framework, peaking at 70% for the most complex graph pairs as they approach the timeout threshold.

Identifying shared sub-circuits is vital for digital design synthesis, verification, and similarity analysis. This paper introduces a novel heuristic for the Maximum Common Subgraph (MCS) problem optimized for large-scale, sparse circuit graphs through two primary contributions. First, we propose an information-dense graph representation using labeled nodes and edges to eliminate redundant vertices, reducing node counts by over 5x and edge counts by 2x without sacrificing expressiveness. These labels effectively prune the search space by highlighting structural incompatibilities. Second, we implement an improved topologically driven heuristic that extends the matching radius and employs a dampening factor to weight node contribution, inspired by message-passing concepts in graph learning. By aggregating information from both fan-in and fan-out cones, we significantly enhance matching accuracy. Experimentally, we introduce an iterative McSplit variant that utilizes adjacency lists to enhance memory efficiency for massive designs. Evaluations on synthetic benchmarks and real-world cases, such as a RISC-V core, demonstrate that our approach substantially outperforms state-of-the-art methods in scalability and practical utility.

The Maximum Common Induced Subgraph problem is a longstanding challenge in graph theory and combinatorial optimization, recognized for being NP-complete and its applications across chemistry, network analysis, and pattern recognition. State-of-the-art methods, such as the McSplit algorithm and its successors, employ a recursive branch-and-bound procedure to navigate the vast solution space. The efficiency of this search is critically dependent on the initial vertex sorting heuristic, which not only guides the algorithm toward a good solution but also structures the search tree for the computationally intensive proof of optimality. The original algorithm relies on a simple node degree heuristic, which is often suboptimal. This paper systematically investigates the influence of alternative vertex-ordering heuristics on McSplitDAL, a state-of-the-art variant of McSplit. We integrate five node-ranking heuristics (namely, PageRank, Betweenness Centrality, Closeness Centrality, Local Clustering Coefficient, and a modified Katz Centrality) into the McSplitDAL framework. We analyze their effect on search-space exploration, pruning efficiency, convergence behavior, and execution speed. We also investigate how they shape the algorithmic search and affect the solver’s ability to approach or prove optimality under constrained computational budgets. Experimental results across heterogeneous datasets reveal that specific heuristics, such as PageRank and Katz Centrality, consistently promote more effective pruning and higher-quality intermediate solutions, offering valuable insights into the relationship between graph topology-derived measures and branch-and-bound performance.

Ensuring the reliability of complex Automotive System-on-Chips (SoCs) is critical. System-Level Test (SLT) is a vital yet relatively new approach that enhances traditional manufacturing tests by running real-world functional programs using specialized Automatic Test Equipment (ATE) and meticulously monitoring the results. A current industrial key challenge is gauging how well these SLT procedures exercise the SoC's resources. This work introduces a novel technique for multicore SoCs, that leverages execution trace analysis. We construct a comprehensive data flow graph by capturing different CPUs instruction traces during SLT. Dynamic analysis of this graph traces each data point to its destination. Our method accounts for inter-core synchronization, providing a holistic view of data flow. A custom metric quantifies overall data flow integrity. Tests on an STMicroelectronics automotive device demonstrate the method's efficiency and quantify significant gains in accuracy, time, and reduced human resources, promising more reliable automotive SoCs.

Developing functional test programs for hardware testing is time-consuming and experience-wise. A functional test program’s quality is usually assessed only through expensive fault simulation campaigns during early development. This paper presents indirect quality measurements of fault detection capabilities of functional test programs to reduce the total cost of fault simulation in the early development stages. We present a methodology that analyzes the instruction trace generated by running functional test programs on-chip and building its control and dataflow graph. We use the graph to identify potential flaws that affect the program’s fault detection capabilities. We present different graph-based techniques to measure the programs’ quality indirectly. By exploiting standard debugging formats, we individuate instructions in the source code that affect the graph-based measurements. We perform experiments on an automotive device manufactured by STMicroelectronics, running functional test programs of different natures. Our results show that our metric allows test engineers to develop better functional test programs without basing their development solely on fault simulation campaigns.

The Maximum Common Subgraph problem has been long proven NP-hard. Nevertheless, it has countless practical applications, and researchers are still searching for exact solutions and scalable heuristic approaches. Driven by applications in molecular science and cyber-security, we concentrate on the Maximum Common Subgraph among an indefinite number of graphs. We first extend a state-of-the-art branch-and-bound procedure working on two graphs to N graphs. Then, given the high computational cost of this approach, we trade off complexity for accuracy, and we propose a set of heuristics to approximate the exact solution for N graphs. We analyze sequential, parallel multi-core, and parallel-many core (GPU-based) approaches, exploiting several leveraging techniques to decrease the contention among threads, improve the workload balance of the different tasks, reduce the computation time, and increase the final result size. We also present several sorting heuristics to order the vertices of the graphs and the graphs themselves. We compare our algorithms with a state-of-the-art method on publicly available benchmark sets. On graph pairs, we are able to speed up the exact computation by a 2× factor, pruning the search space by more than 60%. On sets of more than two graphs, all exact solutions are extremely time-consuming and of a complex application in many real cases. On the contrary, our heuristics are far less expensive (as they show a lower-bound for the speed up of 10×), have a far better asymptotic complexity (with speed ups up to several orders of magnitude in our experiments), and obtain excellent approximations of the maximal solution with 98.5% of the nodes on average.

Many modern applications are modeled using graphs of some kind. Given a graph, assigning labels (usually called colors) to vertices is called graph coloring. Colors must be assigned so that no two vertices connected by an edge share the same color. Graph coloring has essential applications in many different fields, and many scalable algorithms have been proposed to solve it efficiently, such that researchers have recently started experimenting with coloring, even on many-core GPU devices. In our work, we selected, analyzed, implemented, and compared state-of-the-art algorithms suited for multi-core CPU and many-core GPU architectures. Our analysis allowed us to discover the advantages and disadvantages of each algorithm, and enabled us to implement new strategies for those algorithms running on CPU and GPU devices. We propose a new technique based on “value permutation” and “index shifting” that, once applied to the Jones-Plassmann-Luby algorithm can reduce both the runtime and the number of colors. We compare our code on standard graph benchmarks with the two most used state-of-the-art applications, cuSparse’s csrColor and Gunrock’s implementations, and one innovative approach named Atos. We present extensive results in terms of computation time and quality of the solution. We show that our fastest implementation is able to achieve high average speedups on mesh-like graphs, with a geometric mean (harmonic mean) of 3.16x (3.05x) against Gunrock, 4.09x (3.06x) against cuSparse, and 4.45x (2.21x) against Atos. Nonetheless it proves to be significantly less effective on scale-free graphs, winning consistently only against Gunrock, with geometric mean (harmonic mean) speedups of 2.76x (2.71x) against Gunrock, 0.13x (0.11x) against cuSparse, and 0.03x (0.01x) against Atos. Moreover, it produces 47% fewer colors than cuSparse, 7% fewer colors than Gunrock, and 63% more colors than Atos.

Electronics play a significant role in modern society in various areas of our daily lives. Companies producing embedded nano-electronic systems have responded to the ever-increasing demand for high-performance chips with the development and production of structurally complex design, both in terms of the number of gates they are composed of and how they are arranged on the silicon surface. Especially devices intended for safety-critical fields, such as the Automotive field, require a thorough and precise testing process before they are fielded. This paper proposes a correlation analysis between candidate faulty logical gates as possible sources of a given failure identified during the Manufacturing Test Flow and their layout characteristics on the silicon. It is meaningful feedback for manufacturers about the quality of their applied tests. The experimental results are reported for data regarding a production lot of an Automotive System-on-Chip belonging to the SPC58 family produced by STMicroelectronics.

Testing and validation check a hardware device or a software application against the desired design requirements. They are a vital part of all steps of system engineering and typically account for a significant percentage of the overall development cost. This paper presents a novel technique to provide a quick preliminary evaluation of functional test procedures of various natures, ranging from Software-Based Self-Test to Burn-In Functional Stress and System-level tests. We define a new metric called “connectivity”, which is fast to compute and can be used to guide functional program development. The method does not require logic or fault simulations, and it is based on the analysis of the execution trace generated by the functional program. To summarize our process, we first obtain the trace directly from the chip, running the software through a debugger. Then, we create a graph representation of the program data flow. Finally, we analyze the graph to identify instructions that negatively impact the final coverage. We perform experiments on an automotive device manufactured by STMicroelectronics, and we demonstrate the effectiveness of the approach in terms of computation time and beneficial effects on the fault coverage.