The Maximum Common Subgraph (MCS) problem is a fundamental challenge in graph theory. It generalizes the subgraph isomorphism problem and is known to be NP-complete and difficult to approximate. This inherent complexity underscores the need for efficient solutions. This work introduces Hydra-MCS, a novel hybrid CPU-GPU approach that significantly accelerates MCS computation. Our method uses a lightweight metric to accurately estimate the remaining computation (RC) for a given solution. Then it uses this metric to offload computations to the GPU, maintain load balancing, and minimize unnecessary task sharing between threads. We identify the essential information the CPU and GPU must share to optimize performance by carefully analyzing our hybrid implementation. Furthermore, we discuss the substantial advantages of offloading computation to the GPU. Our method establishes a new state of the art in performance. Under matched CPU resources, GPU integration provides approximately a $3\times$ additional speedup over Hydra-MCS CPU and approximately a $4\times$ speedup over parallel McSplit on the scaling workload; across long-running benchmark instances, speedups over McSplit typically reach 4-$5\times$, with peaks exceeding $12\times$. We also address scalability and robustness, as our algorithm's behavior significantly surpasses that of the original as the number of threads increases and the problems become harder. A comprehensive analysis comparing solved instances over time demonstrates that the hybrid implementation consistently solves 30-40% of the instances not yet solved by the original framework, peaking at 70% for the most complex graph pairs as they approach the timeout threshold.

Real-time anomaly detection is pivotal to the success of smart robotics, particularly in production plants, where even minor system failures can result in significant machine downtime and costly process disruptions. To address this, a specialized ML model must be seamlessly integrated into a network of interconnected machinery, sensors, and actuators, all processing vast streams of multidimensional sensor data with minimal latency that cloud-based solutions often struggle to achieve. In this work, we introduce VARADE++, an edge-optimized anomaly detection framework designed to navigate the complex trade-offs between anomaly detection accuracy, inference speed, and computational efficiency. By leveraging a lightweight auto-regressive architecture rooted in attentionless transformers, paired with a variational training paradigm, we achieve real-time processing capabilities. Our model is integrated into an advanced IoT infrastructure, enabling low-latency handling of intricate data streams. The effectiveness of VARADE++ is demonstrated across two public benchmarks and validated through a real-world case study within a sensorized industrial pilot production line, with an industrial robot as the primary focus. Our results not only highlight the superior anomaly detection capabilities of VARADE++ but also showcase its operational efficiency in a real-time edge computing environment, outperforming state-of-the-art solutions in the balance between detection performance and practical deployability.

Identifying shared sub-circuits is vital for digital design synthesis, verification, and similarity analysis. This paper introduces a novel heuristic for the Maximum Common Subgraph (MCS) problem optimized for large-scale, sparse circuit graphs through two primary contributions. First, we propose an information-dense graph representation using labeled nodes and edges to eliminate redundant vertices, reducing node counts by over 5x and edge counts by 2x without sacrificing expressiveness. These labels effectively prune the search space by highlighting structural incompatibilities. Second, we implement an improved topologically driven heuristic that extends the matching radius and employs a dampening factor to weight node contribution, inspired by message-passing concepts in graph learning. By aggregating information from both fan-in and fan-out cones, we significantly enhance matching accuracy. Experimentally, we introduce an iterative McSplit variant that utilizes adjacency lists to enhance memory efficiency for massive designs. Evaluations on synthetic benchmarks and real-world cases, such as a RISC-V core, demonstrate that our approach substantially outperforms state-of-the-art methods in scalability and practical utility.

The proliferation of smart devices with inertial measurement units has driven human activity recognition (HAR) research for several years. However, existing datasets like the Smartphone and Smartwatch Activity and Biometrics Dataset (from the Wireless Sensor Data Mining Lab, i.e., the WISDM Lab) may suffer from non-uniform sampling, missing data, and sensor misalignment. To overcome the limitations mentioned above, we present the Smart Inertial Device Data from Human Activities (SIDDHA) dataset, which is a meticulous reconstruction of the previously described dataset. Our rigorous reconstruction employs a two-phase characterization followed by spline interpolation methods for resampling and filtering, yielding a uniformly sampled and realigned data. An additional key innovation of this process is to include spike-encoded inertial data, generated using eleven distinct encoding techniques. We specifically tailor this process for spiking neural networks and neuromorphic computing. Technical validation confirms SIDDHA’s enhanced quality. Experimental results demonstrate an improved HAR and better accuracy on SIDDHA’s raw data with recurrent architectures such as the Legendre memory unit, and the long short-term memory.

The Maximum Common Induced Subgraph problem is a longstanding challenge in graph theory and combinatorial optimization, recognized for being NP-complete and its applications across chemistry, network analysis, and pattern recognition. State-of-the-art methods, such as the McSplit algorithm and its successors, employ a recursive branch-and-bound procedure to navigate the vast solution space. The efficiency of this search is critically dependent on the initial vertex sorting heuristic, which not only guides the algorithm toward a good solution but also structures the search tree for the computationally intensive proof of optimality. The original algorithm relies on a simple node degree heuristic, which is often suboptimal. This paper systematically investigates the influence of alternative vertex-ordering heuristics on McSplitDAL, a state-of-the-art variant of McSplit. We integrate five node-ranking heuristics (namely, PageRank, Betweenness Centrality, Closeness Centrality, Local Clustering Coefficient, and a modified Katz Centrality) into the McSplitDAL framework. We analyze their effect on search-space exploration, pruning efficiency, convergence behavior, and execution speed. We also investigate how they shape the algorithmic search and affect the solver’s ability to approach or prove optimality under constrained computational budgets. Experimental results across heterogeneous datasets reveal that specific heuristics, such as PageRank and Katz Centrality, consistently promote more effective pruning and higher-quality intermediate solutions, offering valuable insights into the relationship between graph topology-derived measures and branch-and-bound performance.

Ensuring the reliability of complex Automotive System-on-Chips (SoCs) is critical. System-Level Test (SLT) is a vital yet relatively new approach that enhances traditional manufacturing tests by running real-world functional programs using specialized Automatic Test Equipment (ATE) and meticulously monitoring the results. A current industrial key challenge is gauging how well these SLT procedures exercise the SoC's resources. This work introduces a novel technique for multicore SoCs, that leverages execution trace analysis. We construct a comprehensive data flow graph by capturing different CPUs instruction traces during SLT. Dynamic analysis of this graph traces each data point to its destination. Our method accounts for inter-core synchronization, providing a holistic view of data flow. A custom metric quantifies overall data flow integrity. Tests on an STMicroelectronics automotive device demonstrate the method's efficiency and quantify significant gains in accuracy, time, and reduced human resources, promising more reliable automotive SoCs.

The in-circuit test checks whether the board's electrical and electronic components have been correctly soldered when producing printed circuit boards. When such a test is performed using a flying-probe tester, the cost of testing is mainly related to the time required for moving probes over the board and the time necessary for defining such movements, tuning the optimization on the number of devices that will eventually be tested. Since the 2000s, flying probe testing has been gaining popularity. Still, despite its industrial relevance, the research has been impaired by the lack of publicly available benchmarks for testing the new algorithms and comparing the different ideas. This article presents an open test set of realistic boards, ranging from a few thousand to half a million test points, together with a tool for generating more samples. It also presents an optimizer for flying probe tests composed of two separate planners: one global detecting test that could be performed together and reordered to obtain a more efficient probing sequence, and one local, implementing the probe movements and taking care of specific board features. The test set will eventually be used to present a quantitative evaluation of the performance of the proposed approach.

Finding the maximum common induced subgraph is a fundamental problem in computer science. Proven to be NP-hard in the 1970s, it has, nowadays, countless applications that still motivate the search for efficient algorithms and practical heuristics. In this work, we extend a state-of-the-art branch-and-bound exact algorithm with new techniques developed in the deep-learning domain, namely graph neural networks and node embeddings, effectively transforming an efficient yet uninformed depth-first search into an effective best-first search. The change enables the algorithm to find suitable solutions within a limited budget, pushing forward the method’s time efficiency and applicability on larger graphs. We evaluate the usage of the L2 norm of the node embeddings and the Cumulative Cosine Similarity to classify the nodes of the graphs. Our experimental analysis on standard graphs compares our heuristic against the original algorithm and a recently tweaked version that exploits reinforcement learning. The results demonstrate the effectiveness and scalability of the proposed approach, compared with the state-of-the-art algorithms. In particular, this approach results in improved results on over 90% of the larger graphs; this would be more challenging in a constrained industrial scenario.

Developing functional test programs for hardware testing is time-consuming and experience-wise. A functional test program’s quality is usually assessed only through expensive fault simulation campaigns during early development. This paper presents indirect quality measurements of fault detection capabilities of functional test programs to reduce the total cost of fault simulation in the early development stages. We present a methodology that analyzes the instruction trace generated by running functional test programs on-chip and building its control and dataflow graph. We use the graph to identify potential flaws that affect the program’s fault detection capabilities. We present different graph-based techniques to measure the programs’ quality indirectly. By exploiting standard debugging formats, we individuate instructions in the source code that affect the graph-based measurements. We perform experiments on an automotive device manufactured by STMicroelectronics, running functional test programs of different natures. Our results show that our metric allows test engineers to develop better functional test programs without basing their development solely on fault simulation campaigns.

Precise residential load modeling is indispensable for crafting effective demand-side management strategies and simulating realistic household power consumption under diverse conditions. This paper introduces a novel generative framework, leveraging the power of Generative Adversarial Networks (GANs), to synthesize highly realistic daily activity patterns. By training on detailed Italian time-use data, the model captures nuanced behavioral statistics, reflecting the inherent variability of human routines. Furthermore, incorporating conditional generation based on the day of the week allows for contextually rich and adaptable simulations, capturing weekly lifestyle variations. Household power profiles are reconstructed by meticulously mapping the generated activities to the characteristic power signatures of common household appliances, resulting in simulations that exhibit strong concordance with empirical load data at both granular, appliance-level, and aggregated household levels. Critically, our GAN-based approach demonstrably accelerates simulation throughput compared to conventional Markov chain methodologies, enabling the efficient and scalable analysis of complex residential energy scenarios, and opening avenues for real-time applications and large-scale urban energy studies.

This paper presents a proof of concept for a novel evolutionary methodology inspired by core knowledge. This theory describes human cognition as a small set of innate abilities combined through compositionality. The proposed approach generates predictive descriptions of the interaction between elements in simple 2D videos. It exploits well-known strategies, such as image segmentation, object detection, simple laws of physics (kinematics and dynamics), and evolving rules, including high-level classes and their interactions. The experimental evaluation focuses on two classic video games, Pong and Arkanoid. Analyzing a small number of raw video frames, the methodology identifies objects, classes, and rules, creating a compact, high-level, predictive description of the interactions between the elements in the videos.

In recent years, there has been an exponential growth in the size and complexity of System-on-Chip (SoC) designs targeting different specialized applications. The cost of an undetected bug in these systems is much higher than in traditional processors, as it may imply loss of property or life. Despite decades of research on simulation and formal methods for debugging and verification, the problem is exacerbated by the ever-shrinking time-to-market and ever-increasing demand to churn out billions of devices. In this work, we propose VeriBug, which leverages recent advances in deep learning (DL) to accelerate debugging at the Register-Transfer level (RTL) and generates explanations of likely root causes. Our experiments show that VeriBug can achieve an average bug localization coverage of 82.5% on open-source designs and a wide variety of injected bugs.

The Maximum Common Subgraph problem has been long proven NP-hard. Nevertheless, it has countless practical applications, and researchers are still searching for exact solutions and scalable heuristic approaches. Driven by applications in molecular science and cyber-security, we concentrate on the Maximum Common Subgraph among an indefinite number of graphs. We first extend a state-of-the-art branch-and-bound procedure working on two graphs to N graphs. Then, given the high computational cost of this approach, we trade off complexity for accuracy, and we propose a set of heuristics to approximate the exact solution for N graphs. We analyze sequential, parallel multi-core, and parallel-many core (GPU-based) approaches, exploiting several leveraging techniques to decrease the contention among threads, improve the workload balance of the different tasks, reduce the computation time, and increase the final result size. We also present several sorting heuristics to order the vertices of the graphs and the graphs themselves. We compare our algorithms with a state-of-the-art method on publicly available benchmark sets. On graph pairs, we are able to speed up the exact computation by a 2× factor, pruning the search space by more than 60%. On sets of more than two graphs, all exact solutions are extremely time-consuming and of a complex application in many real cases. On the contrary, our heuristics are far less expensive (as they show a lower-bound for the speed up of 10×), have a far better asymptotic complexity (with speed ups up to several orders of magnitude in our experiments), and obtain excellent approximations of the maximal solution with 98.5% of the nodes on average.

Many modern applications are modeled using graphs of some kind. Given a graph, assigning labels (usually called colors) to vertices is called graph coloring. Colors must be assigned so that no two vertices connected by an edge share the same color. Graph coloring has essential applications in many different fields, and many scalable algorithms have been proposed to solve it efficiently, such that researchers have recently started experimenting with coloring, even on many-core GPU devices. In our work, we selected, analyzed, implemented, and compared state-of-the-art algorithms suited for multi-core CPU and many-core GPU architectures. Our analysis allowed us to discover the advantages and disadvantages of each algorithm, and enabled us to implement new strategies for those algorithms running on CPU and GPU devices. We propose a new technique based on “value permutation” and “index shifting” that, once applied to the Jones-Plassmann-Luby algorithm can reduce both the runtime and the number of colors. We compare our code on standard graph benchmarks with the two most used state-of-the-art applications, cuSparse’s csrColor and Gunrock’s implementations, and one innovative approach named Atos. We present extensive results in terms of computation time and quality of the solution. We show that our fastest implementation is able to achieve high average speedups on mesh-like graphs, with a geometric mean (harmonic mean) of 3.16x (3.05x) against Gunrock, 4.09x (3.06x) against cuSparse, and 4.45x (2.21x) against Atos. Nonetheless it proves to be significantly less effective on scale-free graphs, winning consistently only against Gunrock, with geometric mean (harmonic mean) speedups of 2.76x (2.71x) against Gunrock, 0.13x (0.11x) against cuSparse, and 0.03x (0.01x) against Atos. Moreover, it produces 47% fewer colors than cuSparse, 7% fewer colors than Gunrock, and 63% more colors than Atos.

Complexity and performance of Automotive System-on-Chips have exponentially grown in the last decade, also according to technology advancements. Unfortunately, this trend directly and profoundly impacts modern Electronic Design Automation tools, which must handle very large amounts of logic gates. The consequence is an exponential increase in computation times, potentially leading to significant production delays. In the context of Burn-In, to reduce the computing time, the stress specification is often relaxed due to the difficulty of grading extensive pattern sets, and it may result in the insurgence of unstressed circuit zones. As a matter of fact, current Electronic Design Automation software tools provide limited capabilities to effectively quantify stress effectiveness, investigate per-pattern set coverage loss, and compute layout-aware stress metrics. This article proposes a toolchain to overcome the limitations mentioned above. We propose a complete software flow to evaluate Burn-In stress patterns through standard toggle coverage and activity effectively. Together with these standard metrics, this article illustrates how to complement traditional measurement with layout-aware toggle coverage metrics. By exploiting parallel programming paradigms and machine learning algorithms, the proposed toolchain drastically reduces computation time for evaluating traditional stress metrics, and it offers new analysis metrics to test engineers conceiving the Burn-in stress patterns. In addition, the toolchain offers some commodities to superimpose the generated stress from different patterns and visualize it over the SoC layout through a heatmap, providing great benefits to test engineers in charge of composing Burn-In recipes. We validated our toolchain on two industrial devices from STMicroelectronics belonging to the SPC58 and SPC56 families, which include around 20 million and 2.7 million gates, respectively.

In smart grids, consumers can be involved in demand response programs to reduce the total power consumption of their households during the peak hours of the day. Unfortunately, nowadays, utility companies are facing important challenges in the implementation of demand response programs because of their negative impact on the comfort of end-users. In this article, we cluster the different operation modes of household appliances based on the analysis of their power signatures. For this purpose, we implement an autoencoder neural network to create a better data representation of the power signatures. Then, we cluster the different operational programs by using a K-means algorithm fitted to the new data representation. To test our methodology, we study the operation modes of some washing machines and dishwashers whose power signatures were derived from both submeters and nonintrusive load monitoring techniques. Our clustering analysis reveals the existence of multiple working programs showing well-defined features in terms of both average energy consumption and duration. Our results can then be used to improve demand response programs by reducing their impact on the comfort of end-users. Furthermore, end-users can rely on our framework to favor lighter operation modes and reduce their overall energy consumption.