This paper introduces an innovative concept defined herein as the MOSFETHybrid Zero Temperature Coefficient (HZTC) bias point. The HZTC is definedas the ZTC point for two distinct transistor types operating in parallel.The derivation of these new ZTC bias points, which emerge from this novelconfiguration, is conducted using a Design-Oriented three DC-parameterMOSFET model. This user-centric MOSFET model includes the conventionalparameters such as the slope factor n, the threshold voltage VT, andthe specific current IS. The novel HZTC MOSFET model is assessed againstestablished simulation results from 16 nm FinFET technology utilizing twodifferent transistor types. This comparison underscores the model’s accuracyand the valuable insights it provides. Furthermore, leveraging the newly introducedHZTC concept, we propose a self-biased, single-output multi-valuevoltage reference based on the HZTC, which can be implemented in anyCMOS process. This design presents a straightforward alternative for developinga multi-output voltage reference that is suitable for a relatively lowTemperature Coefficient (TCeff). The proposed topology has been designedwithin a 16 nm FinFET CMOS process to yield four programmable outputvoltages: 550 mV, 630 mV, 807 mV, and 905 mV, all under a supply voltageof 1.5 V. The silicon area utilized for this implementation is approximately0.001205 mm² (28 μm x 43.2 μm). Post-layout circuit simulations estimatethat the voltage reference maintains a TCeff consistently below 200 ppm/°Cacross a temperature range of -45 to +85 °C, encompassing all corners of fabrication, with a maximum sensitivity of σ/μ = 1.4% after trimming.

As cybersecurity integrates artificial intelligence (AI), the need for robust hardware-based security mechanisms becomes critical—especially for devices with limited resources such as IoT and edge devices. This chapter presents a comprehensive overview of True Random Number Generators (TRNGs) and Physically Unclonable Functions (PUFs) as building blocks for cryptographic systems. Focusing on the hardware design and implementation of PUF and TRNG circuits, it explores their roles in hardware authentication, static and dynamic entropy generation, and secure key management. The chapter examines entropy evaluation methods, design architectures—including ring oscillators and relaxation-based circuits—and assesses statistical randomness using NIST SP 800-22 and related test suites. Additionally, it presents practical FPGA and CMOS implementations optimized for low-power, high-entropy applications.

This work presents an optimized design of a nano-Watt Schmitt Trigger-based Digital Operational Transconductance Amplifier (ST-DIGOTA) implemented using high voltage devices in 16 nm CMOS FinFET technology. To address the dominant leakage currents that impact ultra-low-power circuits in advanced nodes, I/O devices are employed for the first time in a DIGOTA design as a design strategy to reduce the power consumption. The proposed circuit operates at a 0.3 V supply while driving a 350 pF capacitive load, achieving 6 nW power consumption and a DC gain of 50 dB within a compact $130 \mu m^{2}$ layout area. Compared to prior 16 nm DIGOTA implementations, this represents a significant power reduction while preserving similar gain. Unlike previous state-of-the-art sub-nW OTAs that target only small capacitive loads ($<10 \text{pF}$), this work demonstrates nanowatt-level operation at large capacitive loads, highlighting its suitability for energy-constrained biomedical and IoT applications where bandwidth requirements are modest.

This paper presents a novel StrongARM Latch (SAL) dynamic comparator architecture designed and optimized for high-speed applications. The proposed design mitigates the clock feedthrough issue, enabling an earlier transition into the regeneration phase and thereby achieving significantly high speed of operation compared to the conventional StrongARM latch. The proposed SAL also includes a body-biasing technique to the input transistors which lowers the threshold voltage of the input transistors and boosts transconductance to achieve the best speed, using a deep n-well transistor available in this PDK. The proposed comparator has been designed and simulated in TSMC 16 nm CMOS technology and the results are compared with the available solutions in the literature. The key achievements of this work are 38% faster comparator with a small increase in the energy when compared to the conventional SAL. The proposed design is very beneficial for low voltage applications by delivering an improvement in delay with about the same energy expense of the conventional SAL. The proposed SAL is capable of achieving a delay of 16 ps with an energy per operation of 7.51 fJ.

Physically Unclonable Functions (PUFs) are a promising hardware security primitive for AI-powered Cyber-Physical Systems (AI-CPS), offering low-cost, low-area, tamper-resistant, and unique key generation. However, the lack of a standardized methodology and lack of consensus in PUF performance metric definition does not allow for fair comparisons across designs which can impact their confidence in use for security. This paper presents a systematic analysis methodology for evaluating PUFs at the circuit simulation level. The methodology establishes transient Monte Carlo simulation strategies, structured data extraction and processing, and metric computation. It addresses the nuanced simulation requirements for each performance metric—uniqueness, repeatability, identifiability, reliability, and randomness—ensuring that each is accurately and fairly assessed. A practical explanation using an Arbiter PUF in Cadence® is provided, along with data handling and metric calculation examples in Python. The proposed methodology facilitates reproducibility and comparability across PUF designs.

Utilizing a Design-Oriented 3 DC-Parameter MOSFET model in conjunction with simulation results obtained from a cutting-edge 16 nm FinFET CMOS technology, we investigate the presence of a Zero Temperature Coefficient (ZTC) point in the transistor gate capacitance C-gs and the transition frequency f (T). At these bias points, their temperature coefficients (TCeff) are reported as 5.6 ppm/degrees C and 95 ppm/degrees C, respectively. Additionally, both theoretical and simulation findings suggest that these ZTC points are situated near the optimal balance between transconductance efficiency and speed, represented by the transistor Figure-of-Merit g(m)/I-D center dot f(T), which is the peak of this curve. This research, for the first time, thoroughly examines the temperature characteristics of these two critical concepts, which are undeniably significant in the Radio Frequency (RF) sector, offering valuable guidelines and insights for Integrated Circuits (IC) designers.

Wildfires are complex and destructive events with widespread impacts across several domains. Advances in sensor technology have led to more accurate tools for wildfire management. Existing solutions use airborne and ground-based platforms to monitor wildfire spread, environmental parameters, pollutant concentrations and firefighter health. Post-wildfire research focuses on mapping burned areas and detecting hotspots. This paper proposes the design of an integrated framework for developing a multi-sensor node (MSN), featuring an Alarm Module (AM) and a Thermal Mapping Module (TMM). The AM monitors weather parameters, firefighting assets, and firefighter health, while the TMM detects hotspots, identifying potential reignition zones. The MSN connects to nearby smartphones via Bluetooth Low Energy (BLE) and uses them to transmit sensor data to the Internet, simplifying hardware design and reducing costs. Results demonstrate that the smartphone successfully receives sensor data from the MSN via BLE and transmits it to the Internet.

Using a Design-Oriented 5 DC-Parameter MOSFET model along with simulation results derived from advanced 16 nm technology, we demonstrate that a zero temperature coefficient (ZTC) bias point does not exist in the intrinsic gain of the transistor, represented by gmrds. Instead, it was found that a ZTC zone is present when the transistor operates in a wellsaturated condition. Although some temperature dependence persists within this ZTC zone, it is characterized by a low complementary to absolute temperature (CTAT) behavior, as indicated by an effective temperature coefficient (TCef f) under 100 ppm/. C, i.e., 0.01% per each 1 degrees C. Furthermore, both theoretical analysis and simulation results reveal that the ZTC zone in both strong and weak inversion does not manifest in triode operation due to the pronounced CTAT behavior of r(ds), which is not adequately compensated by the proportional to absolute temperature (PTAT) behavior of g(m). This research highlights the complexities of temperature dependence in MOSFET operations and introduces significant insights into transistor behavior at the nanoscale.

This paper presents an evaluation of the mismatch robustness of Hot Spot Bias Points (HSBP), approached through a simulation-based methodology. The HSBP consists of three distinct bias points: the Zero Temperature Coefficient (ZTC), the Transconductance Zero Temperature Coefficient (GZTC), and the Zero Distortion Bias Point (ZDBP). The ZTC and GZTC are characterized as the MOSFET drain current and transconductance that exhibit insensitivity to temperature variations, while the ZDBP represents the point at which the transconductance achieves its maximum derivative, thus resulting in a zero third-order distortion. Understanding the variability of these bias points under mismatch variations is crucial for guiding Integrated Circuit (IC) designers. Such insights enable designers to leverage the advantages of HSBPs while also recognizing their limitations in terms of robustness. Utilizing a 16 nm FinFET Process Design Kit (PDK), this study investigates several devices. Monte Carlo simulations reveal that, for the minimum (maximum) transistor area of the core device, the following coefficients of variation are sigma ZTC\mu ZTC = 1.78%(0.070%), sigma GZTC\mu GZTC = 2.31% (0.066%), and sigma ZDBP\mu ZDBP = 6.91%(1.87%) for the ZTC, GZTC, and ZDBP, respectively. These metrics are always normalized with respect to the threshold voltage (V-T) of the core device. Furthermore, the robustness of the HSBPs across low voltage scenario is also demonstrated.

This paper meticulously revisits the derivation of the MOSFET Zero Temperature Coefficient (ZTC) and the Transconductance Zero Temperature Coefficient (GZTC) conditions, with a focus on a Design-oriented five DC-parameter MOSFET model, which is an extremely useful tool for handling calculations in IC Design Field. This work proposes the incorporation of two short channel effects in the ZTC and GZTC modeling-namely, the Drain Induced Barrier Lowering (DIBL) effect, denoted as sigma, and the velocity saturation effect, represented by zeta-enhancing the traditional three DC-parameter model, which includes the slope factor n , the threshold voltage V (T), and the specific current I (S). In addition, for the first time, this paper proposes a more comprehensive general closed expression for the ZTC and GZTC points in both triode and saturation regimes, leveraging the Lambert function W (0)( x ). By employing the derived expressions for each phenomenon, the ZTC and GZTC dependence concerning each physical parameter is thoroughly investigated. Furthermore, these theoretical findings are compared with simulated data obtained from a mature 16nm FinFET Process Design Kit (PDK). The results demonstrate that the integration of sigma and zeta into the ZTC and GZTC calculations yields a significant improvement in accuracy, reducing the error between the simulation and the model values from 8% to less than 2%. This enhancement underscores the importance of considering additional effects when analyzing temperature coefficients in MOSFETs, thus providing valuable insights for professionals engaged in advanced IC design.

This paper presents the design and implementation of a robust conventional NMOS-based Low Dropout Regulator (LDO) in 16nm FinFET. The LDO features a recycling folded-cascode as error amplifier with a supply voltage ranging from 1.028V to 1.32V and a programmable output voltage from 0.4V to 0.9V. The primary objective of this work is to achieve the optimal balance between various specifications including DC gain, Power Supply Rejection Ratio (PSRR), silicon area, and line/load regulation response. The robustness of the LDO design was thoroughly validated at the schematic level under 516 Process, Voltage, and Temperature (PVT) corners, as well as through Monte Carlo (MC) Simulations. The designed LDO, occupying an estimated area of 2696.8 μm 2 , demonstrates a mean DC gain of 74.87dB, PSRR at 10kHz of −76.28dB, and PSRR at 1MHz of −36.29db. Additionally, the LDO consistently maintains a phase margin exceeding 65°. The proposed LDO is compared with the current state of the art.

The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD). The MTD will consist of barrel and endcap timing layers, BTL and ETL respectively, providing precision timing of charged particles. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs with TOFHIR2 ASICs for the front-end readout. A resolution of 30–40 ps for MIP signals at a rate of 2.5 Mhit/s per channel is expected at the beginning of HL-LHC operation. We present an overview of the TOFHIR2 requirements and design, simulation results and the first measurements with TOFHIR2A silicon samples.

An ultra-low voltage and power Schmitt-Trigger-Based Digital Operational Transconductance Amplifier (ST-DIGOTA) is proposed here for the first time using 16 nm CMOS FinFET technology. In this design, the inverter gates, whose digital outputs are used to govern the circuit evolution throughout each circuit states, are replaced by Schmitt-Trigger inverters making their own trip points variable. It allows the DIGOTA to stay more time in the states that trigger the output stage increasing then the circuit bandwidth. Similar to others digital-like OTA implementations, the proposed one is designed without the need of any biasing circuit and only used digital standard cells aiming a quick design cycle and porting. For comparison purpose, two DIGOTAs are designed at the same FinFET technology: with (ST-DIGOTA) and without (DIGOTA) Schmitt-Trigger inverters. Even though the ST-DIGOTA floorplan silicon area is 39% larger than DIGOTA, operating at the same supply voltage of only 300 mV, the ST-DIGOTA achieves 70% more Gain-bandwidth product (GBW) and 25dB more DC gain consuming only 451 nW more. Both OTAs are able to drive a capacitive load of 500pF having similar an average slew rate of 2.9 mV/μs for both the ST-DIGOTA and DIGOTA. In light of these results, an area-normalized large signal figure of merit (FOM LA ) of 36k and 352.6k [(V/μs)·pF/(μW·mm 2 )] are accomplished along with an area-normalized small signal figure of merit (FOM SA ) of 0.34M and 1.8M [MHz·pF/(μW·mm 2 )] for ST-DIGOTA and DIGOTA, respectively.

Analog computing is based upon using physical processes to solve formal mathematical problems. In the past, it was the predominant instrument of scientific calculations. Now, as the physical limits imposed on digital devices compel research into alternate computing paradigms, a reexamination of the potentialities of analog computing is warranted. This work studies the application of analog CMOS cells toward the simulation of dynamical systems, and, more generally, solving sets of coupled time-dependent ordinary differential equations. Following a brief review of the fundamentals of systems theory and analog computing, the main set of computing elements is introduced, each comprising analog cells designed in a 130 nm process. These are subsequently applied to the realization of practical, special-purpose analog computing modules. Illustrative systems from various fields are selected for simulation. Though by no means comprehensive, these case studies highlight the capabilities of contemporary analog computing, especially in solving nonlinear problems. Circuit simulations show good agreement with solutions obtained from high-order numerical methods, at least over a limited range of system parameters. The article concludes with a brief discussion of broader analog computing applications, offering future prospects toward further exploration of its potentialities and limitations in a wide range of domains.

A new PETsys ASIC in the TOFPET series, named TOFPET3, has been developed aiming at high performance PET applications. The new chip has a 64-channel analog front-end with baseline stabilization, pulse tail cancelation, dark noise rejection and gain configuration. In each channel, three 10-bit digitization of pulses above a configurable threshold are performed (2 TDC, 1 QDC). The maximum event rate per channel is 500 kHz, and the output bandwidth is $3.8 \mathrm{~Gb} / \mathrm{s}$ matching the input rate. The new timing and energy circuits have outstanding performance: 1) the TOFPET3 contribution to CTR is 26 ps FWHM, implying that a CTR =80(120) ps due to crystal and SiPM, increases to 84(123) ps with TOFPET3; 2) the contribution to 511 keV photopeak resolution is 1.1% and the deviation to linearity is $\pm 1 \%$ in the range 300-3000 p.e for SiPM gain $3.5 \times 10^{6}$. Charge integration of single photons is possible with $\mathrm{S} / \mathrm{N}\gt10$. The chip includes four additional channels with sums of 16,32 or 64 cannels (configurable) suitable for light sharing applications, as well as advanced triggering features allowing the selective readout of a group of channels triggered by the energy of one channel. The power consumption is 8 mW per channel. In this summary we present simulation results of the chip performance. At the conference, measurements with the prototype chip will be presented.

Security and authentication of low-power embedded systems for the internet of things (IoT) is a research topic that is growing due to the extensive numbers of devices. Modern biomedical devices configured and calibrated wirelessly are very specific embedded systems with limited power and processing capacity, but with security challenges requiring low-power and robust security. This paper presents a review of security solutions based on Physical Unclonable Functions (PUF) for medical devices and the major hardware challenges to design a robust PUF. We discuss modern hardware solutions for weak and strong PUFs and how they are implemented in modern CMOS technology. Three PUFs with entropy sources based on relaxation oscillators and ring oscillators (ROPUFs), implemented in 130 nm CMOS technology are presented. The proposed self-biased RO improved the sensitivity to PV variations. The coupled relaxation oscillator obtained a power consumption of 10.56 mW. Additionally, we discuss how the process, supply voltage, and temperature (PVT) variations affect the PUF performance.

In this paper, it is proposed an entropy source based on oscillators for a robust implementation in hardware of True Random Number Generators. The innovative techniques used are: self-biasing is applied to a standard ring oscillator, and a noise amplification scheme at the output of the oscillators. The jitter noise is harvested and analyzed, to understand the potential of the proposed circuit as a dynamic entropy source for a TRNG. The proposed circuit is compared to a standard ring oscillator, both designed in a 130 nm standard CMOS technology using a 1.2 V supply. Simulated results are presented to verify the efficiency of the proposed self-biased ring oscillator. The simulations showed a power consumption reduction of approximately 60% compared to the standard approach. At the same time, it had a frequency of 127.2 MHz, a jitter standard deviation of 1.72 ns for the entropy source, and 4.27 ns for the complete circuit. Furthermore, the proposed circuit presented a throughput of 121 Mb/s, and outperformed the standard ring oscillator based TRNG in terms of randomness, for the NIST tests possible to perform, considering the extracted bits, it proved to be successful in all of them, even under temperature and voltage supply variations. Thus, it demonstrates the potential to be used as a TRNG, in many IoT applications.

To effectively manage the terrestrial firefighting fleet in a forest fire scenario, namely, to optimize its displacement in the field, it is crucial to have a well-structured and accurate mapping of rural roads. The landscape’s complexity, mainly due to severe shadows cast by the wild vegetation and trees, makes it challenging to extract rural roads based on processing aerial or satellite images, leading to heterogeneous results. This article proposes a method to improve the automatic detection of rural roads and the extraction of their centerlines from aerial images. This method has two main stages: (i) the use of a deep learning model (DeepLabV3+) for predicting rural road segments; (ii) an optimization strategy to improve the connections between predicted rural road segments, followed by a morphological approach to extract the rural road centerlines using thinning algorithms, such as those proposed by Zhang–Suen and Guo–Hall. After completing these two stages, the proposed method automatically detected and extracted rural road centerlines from complex rural environments. This is useful for developing real-time mapping applications.

Nowadays cryptography is increasingly more important, not only to keep communications safe but also to authenticate users and devices alike. A few years ago, most of the algorithms and cryptographic systems available to the public were implemented in software. However currently one of the best ways to tackle this problem is using specific hardware to produce a random output. In this paper we present an investigation to different True Random Number Generator (TRNG) architectures, implemented in a Field Programmable Gate Array (FPGA), based on ring oscillators and the results of a specific set of tests developed to verify the resilience and randomness characteristics of random number generators, NIST SP800-22R. Our objective is to create a dynamic entropy generator based on standard Ring Oscillators using the lowest number of resources possible. The tests ran using a 10 Mbytes sample stored in a .txt file received from the FPGA with the size of 1 kbytes and 7000 bitstreams (number of times the 1 kbytes will be tested). The best performing configuration only uses 160 gates. But it is possible to reduce by almost a third the number of gates and still get on the 5th best performing configuration with a higher efficiency.

In this paper we present a dynamic entropy generator based on the oscillator jitter, which uses a self-biasing technique to minimize process, voltage, and temperature (PVT) variations. The proposed circuit has the advantage of its intrinsic robustness due to self-biasing design, which eliminates the need of additional calibration steps and simplifies the circuit topology, with a negligible impact in area and power consumption. A frequency deviation below 15 % and a maximum jitter difference of 32 % under PVT variations, is obtained, in a 28 nm CMOS technology circuit prototype. For validation of the proposed circuit technique the IC prototype is compared with a standard ring oscillator and with traditional calibration techniques.