This work aims to the analysis of high-voltage (HV) SiC MOSFETs' reliability and robustness. Large-area (up to 25 mm(2) ) devices rated for 1.7-, 3.3-, and 4.5-kV applications were fabricated with a special process for gate oxide formation aimed to improve channel mobility. This treatment consists of the incorporation of boron atoms into the SiO2/SiC interface. The unit cell was designed to achieve a good short-circuit performance. As voltage rating increases, the reliability and robustness of power devices are crucial. Nevertheless, the procedures to test and characterize wide bandgap (WBG) power devices are still not standardized. In this work, the V-th drift was evaluated at room temperature and at high temperature using a gate stress test specific for SiC devices. Switching at high bus voltage, short-circuit and power cycling were considered as reliability tests. Test results put in evidence that fabricated devices show reasonably good robustness but suffer from a significant Vth drift caused by the boron process added to the gate oxide formation.

In this work, we have evaluated 4° off-axis Si face 4H-SiC MOSFETs channel performance along both the [11-20] (perpendicular to steps) and [1-100] (parallel to steps) orientations, to evidence possible anisotropy on Si-face due to roughness scattering effect. Improved gate oxide treatments, allowing low interface state densities and therefore high mobility values, have been used on both NO and N2O annealed gate oxides. With these high channel mobility samples, a small anisotropy effect (up to 10%) can be observed at high electric fields. The anisotropy can be seen both at room and high temperatures. However, the optical phonon scattering is the dominant effect under these biasing conditions.

This work addresses the electrical behaviour of high-voltage (HV) SiC MOSFETs, being the main motivation to check their robustness. Large area (25 mm 2 ) devices rated for 3.3 kV applications were fabricated with a special process for the gate oxide formation. The unit cell was designed to achieve good short-circuit performance. Static and dynamic characterization is presented at room and high temperature. Output curves and 3 rd quadrant behaviour were analysed. Dynamic tests were performed at high bus voltages and high current. To check device robustness, short-circuit and power cycling’s were considered. Robustness test results put in evidence the achievement of reasonable good results obtained due to a suitable cell design.

In previous works, an alternative gate oxide configuration, based on a boron treatment, was proposed in order to enhance the SiO2/SiC interface quality, enabling high channel mobility n-channel 4H-SiC lateral MOSFETs. In this paper we study the effect of this treatment on 6H-SiC MOSFETs and we compare it to their 4H-SiC counterparts. The gate oxide boron treatment highly increases mobility values in 4H-SiC whereas the increase is lower in 6H-SiC. The mobility increase by the boron treatment in 4H-SiC MOSFETs is related to the decrease of near interface oxide traps (NIOTs). Then, a different NIOTs density and energy location can be seen as a possible explanation for the different mobility improvement behavior seen in both polytypes.

It is widely known that devices based on wide gap semiconductors show potential benefits in terms of saving mass, increasing power densities compared with standard Silicon ones [1]. The higher operating temperatures these components can withstand can also reduce the power budget currently used for cooling down power electronics. These factors are critical in space applications where, for example SiC devices are very promising. However, in this field reliability is a paramount requirement, and radiation conditions can compromise the usage of these new technologies.

This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO 4 . We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO 2 , thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO 2 interlayer and a Zr x Si y O z (theoretical Si/Z=0.7) layer on top.

This paper reviews advanced gate dielectric processes for SiC MOSFETs. The poor quality of the SiO2/SiC interface severely limits the value of the channel field-effect mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation methods are effective in increasing the channel mobility and have been adopted by manufacturers for the first generations of commercial power devices. Gate oxide doping techniques have also been successfully implemented to further increase the channel mobility, although device stability is compromised. The use of high-k dielectrics is also analyzed, together with the impact of different crystal orientations on the channel mobility. Finally, the performance of SiC MOSFETs in harsh environments is also reviewed with special emphasis on high temperature operation.

The fabrication of CMOS devices in SiC is important for both a higher operating temperature capability and the integration with SiC power devices. In this work, n-channel and p-channel signal MOSFETs have been successfully fabricated using a process technology fully compatible with our HV SiC VDMOS technology. A preliminary SiC CMOS inverter has been also integrated. The gate oxide configuration includes the use of Boron to improve SiO 2 /SiC. Electrical characterizations have been carried out at room temperature and a summary of the results is presented. The biggest challenge is to balance the n-type and p-type MOSFETs not only in area but also in V th value.

In this paper, the impact of temperature and time stress on gate oxide stability of several multi-implanted and epitaxied 4H-SiC nMOSFET is presented. The oxide layer was processed under a rapid thermal process (RTP) furnace. The variation of the main electrical parameters is shown. We report the high quality and stability of such implanted MOSFETs, and point out the very low roughness effect of the on-axis-cut sample. Particularly, in the best case, effective channel mobility (μfe) overcomes 20 cm2.V−1.s−1 at 300 °C for a channel length of 12 μm, which is very encouraging for implantation technology. Starting from 200 °C, the apparent increase of the μfe peak of the MOSFET ceases and tends to saturate with further temperature increase. This is an indication of the potential of MOSFETs built on on-axis substrates. Thus, starting from the real case of an implanted MOSFET, the global purpose is to show that the electrical performance of such an on-axis-built device can tend to reach that of the ideal case, i.e. epitaxied MOSFET, and even overcome its electrical limitation, e.g. in terms of threshold voltage stability at high temperature.

An alternative gate oxide configuration is proposed to enhance the SiO2/SiC interface quality, enabling high mobility 4H-SiC lateral metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxide is prepared by the combination of rapid thermal oxidation in N2O ambient, boron diffusion into SiO2, and plasma enhanced chemical vapor deposition of tetraethyl orthosilicate oxide. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurements on fabricated capacitors reveal a reduction of both interface trap and near interface oxide trap densities. The fabrication of MOSFETs with very high field-effect mobility (μfe) values, up to 160 cm2/V s, is enabled. Several channel orientations, with respect to the wafer flat {112¯0}, have been studied to check μfe values and isotropy. Higher μfe values are obtained for a channel orientation of 90°. Boron distribution is studied by secondary ion mass spectrometry (SIMS) and time of flight SIMS. We propose that the combination of boron and nitrogen induces changes in the structure of the gate oxide which are positive in terms of the SiO2/SiC interface quality.

A new gate oxide configuration, including a Boron treatment, is reported in this work. It is designed to improve the SiO 2 /SiC interface quality in 4H-SiC N-MOSFETs. The obtained results show high field effect mobilities up to 160 cm 2 /Vs. The fabricated devices have also been undergone to a BSI stress up to 20 h at room temperature showing good threshold voltage stability. The physical (SIMS) analysis of the oxide and SiC surface reveals that Boron has not diffused into the SiC.

Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit capability and switching performance are analyzed together with design strategies for their improvement. Finally, the limits of high voltage MOSFETs are outlined and future power devices to overcome the MOSFETs limits in ultra-high voltage applications are presented.

A new process technology for 4H-SiC planar power MOSFETs based on a boron diffusion step to improve the SiO2/silicon carbide interface quality is presented in this paper. Large area (up to 25 mm(2)) power MOSFETs of three voltages ratings (1.7, 3.3, and 4.5 kV) have been fabricated showing significant improvements in terms of inversion channel mobility and on-resistance in comparison with counterparts without boron oxide treatment. Experimental results show a remarkable increase of the channel mobility, which raises the device current capability, especially at room temperature. When operating at high temperature, the impact of the high channel mobility due to boron treatment on electrical forward characteristics is reduced as the drift layer resistance starts to dominate in the total on-state resistance. In addition, the third quadrant characteristics approximate to those of an ideal PiN diode, and the device blocking capability is not compromised by the use of boron for the gate oxide formation. The experimental performance in a simple dc/dc converter is also presented.

A new oxide configuration for the development of high mobility 4H-SiC lateral MOSFETs is proposed in this work. The oxide is composed by a rapid thermal oxidation (RTO) in N 2 O environment, a Boron diffusion into the SiO 2 and a PECVD TEOS deposited oxide, in order to improve the interface quality. The obtained MOSFETs show very high peak field effect mobilities ranging from 80 up to more than 170 cm 2 V -1 s -1 in MOSFETs with higher channel length than the tested transistors. The physical (SIMS) and electrical analysis of the oxide and SiC surface reveals that the Boron has not diffused into the SiC. This is most probably due to the high concentration of Nitrogen at the interface generated during the N 2 O oxidation.

A new process based on Boron diffusion step to improve the SiO 2 /SiC interface quality is presented in this work. Surprisingly, Boron, a p-type dopant and small size atom, generates similar apparent improvements as previous oxide treatments based on large size atoms, n-type or deep levels dopants. This process has been applied to a thermal oxide grown to fabricate large area (up to 25mm 2 ) 4.5kV 4H-SiC VDMOS. Fabricated devices show a significant improvement in terms of channel effective mobility, on-resistance, and 3 rd quadrant behavior in comparison with counterparts without Boron oxide treatment.

SiC planar VDMOS of three voltages ratings (1.7 kV, 3.3 kV and 4.5 kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO 2 /SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

The electrical behaviour of irradiated and post-irradiation annealed nMOSFETs with an implanted p-type body and having a N 2 O oxynitrided gate oxide is analysed in this work. This study reveals the existence of a “threshold fluence” which might change the predominant SiO 2 /SiC interface charge trapping type from donors to acceptors at a given energy. The irradiation fluence and energy limit that guaranty a normal or improved operation of the MOSFETs are also given.