This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.

Modest channel carrier mobility in SiC-MOSFETs with NO annealed gate oxides has been the main factor hampering development of low power devices (300 – 650 V). A very fast interface trap, noted as NI, has been suggested to be the main culprit for poor inversion channel carrier mobility. The origin of the NI trap is unknown, but it is likely a property of the SiO 2 and it is enhanced during post nitridation. In this study we show that the NI trap is also detected in 4H-SiC/AlN and 4H-SiC/Al 2 O 3 MIS-capacitors. Observations are done using conductance spectroscopy and capacitance voltage measurements at cryogenic temperatures. This strongly suggests that the NI trap is a property of the SiC surface and not the dielectric used to form the SiC/dielectric interface. Furthermore, a scanning transmission electron microscopy (STEM) was performed to confirm that there are no SiO 2 layers or islands present at the 4H-SiC/AlN and 4H-SiC/Al 2 O 3 interfaces.

Modest channel carrier mobility in SiC-MOSFETs with NO annealed gate oxides has been the main factor hampering development of low power devices (300 – 650 V). A very fast interface trap, noted as NI, has been suggested to be the main culprit for poor inversion channel carrier mobility. The origin of the NI trap is unknown, but it is likely a property of the SiO2 and it is enhanced during post nitridation. In this study we show that the NI trap is also detected in 4H-SiC/AlN and 4H-SiC/Al2O3 MIS-capacitors. Observations are done using conductance spectroscopy and capacitance voltage measurements at cryogenic temperatures. This strongly suggests that the NI trap is a property of the SiC surface and not the dielectric used to form the SiC/dielectric interface. Furthermore, a scanning transmission electron microscopy (STEM) was performed to confirm that there are no SiO2 layers or islands present at the 4H-SiC/AlN and 4H-SiC/Al2O3 interfaces.

Very fast interface traps have recently been suggested to be the main cause behind poor channel-carrier mobility in SiC metal–oxide–semiconductor field effect transistors. It has been hypothesized that the NI traps are defects located inside the SiO2 dielectric with energy levels close to the SiC conduction band edge and the observed conductance spectroscopy signal is a result of electron tunneling to and from these defects. Using aluminum nitride and aluminum oxide as gate dielectrics instead of SiO2, we detect NI traps at these SiC/dielectric interfaces as well. A detailed investigation of the NI trap density and behavior as a function of temperature is presented and discussed. Advanced scanning transmission electron microscopy in combination with electron energy loss spectroscopy reveals no SiO2 at the interfaces. This strongly suggests that the NI traps are related to the surface region of the SiC rather than being a property of the gate dielectric.

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

We investigate the impact of power MOSFET channel width on the power efficiency of a switch-mode power supply. With this analysis, we derive a circuit-specific criterion that minimizes the power dissipated by a power MOSFET, which is based on the ratio between on resistance and output capacitance of the MOSFET and is independent of its technological parameters. The effect of channel width on the power dissipation is illustrated by simulation-based analysis, which also provide an example of a published non-optimum selection of a power MOSFET and demonstrate the advantage of the newly proposed method for MOSFET selection.

Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.

The channel carrier mobility in commercially available 4H-SiC MOSFETs with NO annealed gate oxides is still far below the theoretical limit. It has been suggested that the main reason is high density of very fast interface traps, labeled NI, located inside the oxide very close to the SiC conduction band edge. The NI traps are usually not observed at room temperature but can be detected at cryogenic temperatures. In this study we use conductance spectroscopy and high-low CV analysis of MOS-capacitors at cryogenic temperatures to show that the very fast NI traps are practically absent in oxides grown using sodium enhanced oxidation.

Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed.

The channel carrier mobility in commercially available 4H-SiC MOSFETs with NO annealed gate oxides is still far below the theoretical limit. It has been suggested that the main reason is high density of very fast interface traps, labeled NI, located inside the oxide very close to the SiC conduction band edge. The NI traps are usually not observed at room temperature but can be detected at cryogenic temperatures. In this study we use conductance spectroscopy and high-low CV analysis of MOS-capacitors at cryogenic temperatures to show that the very fast NI traps are practically absent in oxides grown using sodium enhanced oxidation.

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

The integration of micro- and nanoelectronics into or onto biomedical devices can facilitate advanced diagnostics and treatments of digestive disorders, cardiovascular diseases, and cancers. Recent developments in gastrointestinal endoscopy and balloon catheter technologies introduce promising paths for minimally invasive surgeries to treat these diseases. However, current therapeutic endoscopy systems fail to meet requirements in multifunctionality, biocompatibility, and safety, particularly when integrated with bioelectronic devices. Here, we report materials, device designs, and assembly schemes for transparent and stable cubic silicon carbide (3C-SiC)-based bioelectronic systems that facilitate tissue ablation, with the capability for integration onto the tips of endoscopes. The excellent optical transparency of SiC-on-glass (SoG) allows for direct observation of areas of interest, with superior electronic functionalities that enable multiple biological sensing and stimulation capabilities to assist in electrical-based ablation procedures. Experimental studies on phantom, vegetable, and animal tissues demonstrated relatively short treatment times and low electric field required for effective lesion removal using our SoG bioelectronic system. In vivo experiments on an animal model were conducted to explore the versatility of SoG electrodes for peripheral nerve stimulation, showing an exciting possibility for the therapy of neural disorders through electrical excitation. The multifunctional features of SoG integrated devices indicate their high potential for minimally invasive, cost-effective, and outcome-enhanced surgical tools, across a wide range of biomedical applications.

Fast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy.

The inversion channel electron mobility in 4H-SiC MOSFETs with NO annealed gate oxides is still well below its theoretical limit. The physical reason behind the reduced mobility is not yet fully established but has for example been attributed to a high density of very fast interface traps close to the conduction band edge. These traps are not detected by high-low CV analysis at room temperature but are observed by conductance spectroscopy at low temperatures. In this study we demonstrate how conventional high-low CV analysis of MOS capacitors at cryogenic temperatures can be applied to detect and quantify these very fast traps.

The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO2 interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers.

Characterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.

The state-of-the-art technology for gate oxides on SiC involves the introduction of nitrogen to reduce the density of interface defects. However, SiC metal–oxide–semiconductor (MOS) field-effect transistors still suffer from low channel mobility even after the nitridation treatment. Recent reports have indicated that this is due to near-interface traps (NITs) that communicate with electrons in the SiC conduction band via tunneling. In light of this evidence, it is clear that conventional interface trap analysis is not appropriate for these defects. To address this shortcoming, we introduce a new characterization method based on conductance–temperature spectroscopy. We present simple equations to facilitate the comparison of different fabrication methods based on the density and location of NITs and give some information about their origin. These techniques can also be applied to NITs in other MOS structures.

Oxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs.

This paper reviews the feasibility of the state-of-the-art electrical techniques adopted from Si technology for characterization of SiC MOS devices. The inability of these conventional characterization techniques to correctly evaluate the trap capture cross section and field-effect mobility in SiC MOS devices are investigated and explained. As near-interface traps (NITs) are an important cause of field-effect mobility degradation in SiC MOS devices, which is different from the impact of interface traps in Si devices, these characterization techniques are unable to produce meaningful results. Therefore, special care is required when measuring these NITs in SiC MOS devices. Due to the quantum confinement effect, the NITs located above the conduction band edge are able to capture and release channel electrons from the conduction band via tunnelling. Recent characterization techniques, specifically designed for SiC MOS devices, measure the NITs above the bottom of conduction band and consider the quantum confinement effect to find the energy position of the NITs. These recent characterization techniques are presented in the later part of the paper.