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The dominant degradation mechanisms in submicron CMOS devices have been identified as hot-carrier induced stress and may affect performance and reliability of VLSI circuits. The physical mechanisms responsible for the generation of the hot-carriers and its effects on device parameters must be clearly understood in order to model the degradation effects on circuit parameters forming part of the VLSI circuit. Using substrate current as a monitor and employing circuit level simulations over a typical operating cycle, the hot-carrier stress on MOS devices and its degradation effects have been modeled. Our investigations have shown that the transistors in a VLSI circuit do not receive the same amount of hot-carrier stress when operated under dynamic operating conditions. It was seen that the stress levels on the transistors during dynamic operation is a complex function of its location, terminal voltages, current magnitudes and duty cycle. The circuit performance may degrade considerably or the circuit itself may fail due to the stress levels experienced by one or more critical devices in the circuit. Using the technique described, it is possible to identity those critical devices having higher levels of stress and it is possible to apply design improvements which could reduce the stress and hence improve reliability. We present an advanced design method which was used to reduce stress levels of identified critical devices in a standard CMOS circuit thereby improving circuit reliability and performance. A life-time model was used to predict improvements in expected operational life of the circuit after design improvements. This method could be extended to other types of circuits and subsystems used in VLSI circuits.

We report on the space charge spectroscopy studies performed on thermally treated melt-grown single crystal ZnO. The samples were annealed in different ambients at 700 °C and also in oxygen ambient at different temperatures. A shallow donor with a thermal activation enthalpy of 27 meV was observed in the as-received samples by capacitance-temperature, CT scans. After annealing the samples, an increase in the shallow donor concentrations was observed. For the annealed samples, E27 could not be detected and a new shallow donor with a thermal activation enthalpy of 35 meV was detected. For samples annealed above 650 °C, an increase in acceptor concentration was observed which affected the low temperature capacitance. Deep level transient spectroscopy revealed the presence of five deep level defects, E1, E2, E3, E4, and E5 in the as-received samples. Annealing of the samples at 650 °C removes the E4 and E5 deep level defects, while E2 also anneals-out at temperatures above 800 °C. After annealing at 700 °C, the T2 deep level defect was observed in all other ambient conditions except in Ar. The emission properties of the E3 deep level defect are observed to change with increase in annealing temperature beyond 800 °C. For samples annealed beyond 800 °C, a decrease in activation enthalpy with increase in annealing temperature has been observed which suggests an enhanced thermal ionization rate of E3 with annealing.

Deep level transient spectroscopy (DLTS) and Laplace-DLTS have been used to investigate the defects created in Sb doped Ge after irradiation with 2MeV protons having a fluence of 1×1013protons/cm2. The results show that proton irradiation resulted in primary hole traps at EV +0.15 and EV +0.30eV and electron traps at EC −0.38, EC −0.32, EC −0.31, EC −0.22, EC −0.20, EC −0.17, EC −0.15 and EC −0.04eV. Defects observed in this study are compared with those introduced in similar samples after MeV electron irradiation reported earlier. EC −0.31, EC −0.17 and EC −0.04, and EV +0.15eV were not observed previously in similar samples after high energy irradiation. Results from this study suggest that although similar defects are introduced by electron and proton irradiation, traps introduced by the latter are dose dependent.

The electronic properties of defects introduced unintentionally, during electron beam deposition (EBD) of Ti and Mo on Cz grown, B-doped Si and those deliberately introduced by proton and electron irradiation are presented in this paper. Deep level transient spectroscopy (DLTS) studies on the samples revealed the following primary hole traps at 0.32 eV and 0.54 eV above the valence band after EBD processing, 0.15 eV, 0.32 eV after proton irradiation and 0.17 eV, 0.23 eV, 0.33 eV and 0.60 eV after electron irradiation. The comparison of the defect levels showed one common defect level at 0.32 eV above the valence band in the three radiation processed samples, and this hole trap is boron related. Most of the defect levels, created in these three samples, are not similar. Higher defect introduction rates were recorded for the proton when compared to the electron irradiation induced primary deep level states. We have also briefly discussed the annealing behaviour of these primary defect levels.

We have used deep level transient spectroscopy (DLTS), and Laplace-DLTS to investigate the defects created in antimony doped germanium (Ge) by sputtering with 3keV Ar ions. Hole traps at EV+0.09eV and EV+0.31eV and an electron trap at EC−0.38eV (E-center) were observed soon after the sputtering process. Room temperature annealing of the irradiated samples over a period of a month revealed a hole trap at EV+0.26eV. Above room temperature annealing studies revealed new hole traps at EV+0.27eV, EV+0.30eV and EV+0.40eV.

It is well known that hot-carriers can cause damage to the interface of silicon MOS devices. Sub-micron and nano-channel nMOS devices have a higher electron temperature in the channel leading to increased impact-ionisation and enhanced interface degradation and damage. During dynamic operation of the nMOS device, hot-electron and hot-hole injections may take place giving rise to greater interface damage. Hot electrons produced due to impact ionisation also generate secondary electron–hole pairs in Si substrate. The visible light is generated by radiative recombination between the secondary hot electrons and hot holes. An optimised substrate current model was developed, the model was used to plot substrate current for a sub-micron nMOS transistor and was compared with the actual measurements carried out on similar device. It was found that the substrate current model can be used as a reliable monitor for impact ionisation damage in MOS devices.

A study of defects introduced during metalisation by electron beam deposition (EBD) process and those introduced by MeV proton irradiation of boron doped p-type Cz grown silicon is presented. We have observed the following hole traps at, 0.32 ± 0.01 eV and 0.54 ± 0.01 eV above the valence band, induced during EBD processing of Titanium/Molybdenum (Ti/Mo) Schottky contacts on our samples. The annealing studies further revealed hole traps at, 0.15 ± 0.02, 0.23 ± 0.01, 0.38 ± 0.01 and 0.59 ± 0.01 eV each above the valence band. After all the defects were annealed out, the sample was irradiated with 2 MeV protons at room temperature and two primary hole traps, 0.15 eV and 0.32 eV were observed. The complete defect structure was then obtained by studying the defect annealing behaviour as well as the depth profiles of the defects.

We have measured the electrical characteristics of electron irradiation-induced defects in n-type (1 1 0), (1 1 1) and (1 0 0) germanium doped with antimony (Sb) by deep-level transient spectroscopy (DLTS) and Laplace-DLTS. The following electron traps at 0.04, 0.15, 0.20, 0.21, 0.23, 0.31 and 0.38 eV below the conduction band were observed and two hole traps at 0.09 and 0.30 eV above the valence band were recorded in the low doping (1014 cm−3) samples. In the higher doping (1015 cm−3) samples, similar electron traps were observed but the electron trap at 0.04 eV below the conduction band and hole trap at 0.09 eV above the valence band was not observed. The electron trap at 0.38 eV is identified as the (V–Sb)−−/− center and the hole trap at 0.30 eV assigned the (V–Sb)0/− appeared in almost equal concentrations in the higher-doped samples but in the lowest-doped samples the hole trap (V–Sb)0/− was more dominant. We have also presented the annealing behavior of these electron-induced defects.

When using Schottky barrier diodes (SBDs) on silicon (Si) to study the thermal stability of radiation-induced defects, point defects injection into the silicon substrate can occur at temperatures where silicidation occurs. These injected point defects can react with the radiation-induced defects and may lead to an incorrect picture of annealing studies of these defects. In order to overcome this problem, we have annealed (1) ruthenium (Ru), cobalt (Co), nickel (Ni) and platinum (Pt) SBDs to form stable silicides on phosphorus (P) doped Si and (2) have measured the electrical characteristics of defects introduced during diodes fabrication by electron beam deposition (EBD), using conventional and (high resolution) Laplace (L-) deep level transient spectroscopy (DLTS). A primary electron trap at 0.48eV below the conduction band was observed after EBD processing of the contacts. Isochronal annealing of the SBDs at 350°C, annealed-in defects 0.05, 0.09, 0.18 and 0.28eV below the conduction band. All the EBD-induced defects were removed after annealing at 600°C. Primary defect depth profile versus annealing temperature results are also presented in this study.

In this study we have investigated the thermal stability (in the range 100 oC - 900 oC) of defects introduced in p-Si by electron beam deposition (EBD) of Ti and Ti/Mo Schottky contacts. The depletion regions below these contacts were probed by conventional deep level transient spectroscopy (DLTS) as well as Laplace (high-resolution) DLTS (L-DLTS). We have chosen Ti as the Schottky contact because the barrier height of Ti/p-Si (0.53 eV) is close to that of TiSi2/p-Si (0.50 eV) that forms after annealing at 600 – 650 oC. The Mo was added on top of the Ti in order to prevent annealing degradation. These contacts were annealed in Ar at temperatures of up to 900 oC in 100 oC steps for half-hour periods. Current – voltage (I-V) and capacitance – voltage (C-V) measurements were used to monitor the quality of the Schottky contacts. DLTS was performed after each annealing cycle to monitor the presence of the EBD-induced defects and to obtain heir electronic properties. We have found that that the Ti/Mo contacts were superior to the Ti contacts. Their (Ti/Mo) barrier height after EBD was 0.52 eV and it gradually increased to 0.56 eV after annealing at 500 oC - 600oC and then dropped to 0.50 eV annealing at 700 oC. DLTS revealed that the main defects introduced during metallization are hole traps H(0.17), H(0.23), H(0.37) and H(0.49). Annealing at 350 oC introduced an additional hole trap H(0.39). After annealing at 550 oC all defects were removed from the depletion region.

The performance and reliability of submicron CMOS circuits have been affected by hot-carrier stress induced degradation. Three common forms of CMOS latch circuits designed using a 0.7-micron commercial process have been considered in a comparative study of the stress levels experienced by individual devices in the circuit. Average stress levels on all the devices over a typical simulation cycle was used to assess the life-time and the reliability of the circuits. We describe a technique that was used to identify the devices having higher than normal stress which may consequently degrade at a faster rate than other devices leading to an early failure of the circuit. We have developed design techniques that can be used to reduce the stress levels in identified devices. The improvements in life-time and reliability have been assessed and analysed. The best circuit configuration to reduce hot-carrier stress induced degradation has been identified. (C) 1998 Elsevier Science Ltd. All rights reserved.