Accelerated temperature lifetesting at Tchannel of 240, 255, and 270°C was performed on 0.1-μm Pt-sunken InP HEMT low-noise amplifiers fabricated on 100 mm InP substrates. The reliability performance was evaluated based on ΔS21 <; -1 dB at 35 GHz. The lifetesting results exhibit activation energy of approximately 1.8 eV and lifetime projection of 99% reliability and 90% confidence exceeds 1 × 108 hours at Tchannel of 125°C. The high reliability demonstration of 0.1-μm Pt-sunken gate InP HEMT low-noise amplifiers on 100 mm InP substrates is essential for advanced military/space applications requiring high reliability performance.

Good ohmic contacts with both low contact resistance and smooth surface morphology are required for the development of a robust manufacturing process of AlGaN/GaN based high power, high frequency MMICs. This extended abstract provides an optimization of the Ti/Al/Ni/Au ohmic metal stacks on AlGaN/GaN HEMT structures with a focus on the thickness of Ni and Au layer. It is found that the Ni thickness is the dominant factor to affect the contact resistance, while the Au thickness affects the surface morphology significantly. An optimal metal stack including a thick Ni and thin Au layer is found, which produces a low contact resistance around 0.26 ohm mm and a smooth surface morphology with a surface roughness of 22nm. An excellent edge acuity is observed. Initial device results from optimized ohmic metal stack are also discussed.

Reliability performance of 0.1-μm Pt-sunken gate InP HEMT MMICs on 4-inch InP substrates was evaluated under elevated temperature life testing. The primary degradation mechanism was observed to be the progressive Schottky junction reaction with the Schottky barrier InAlAs and the InGaAs channel. Despite the progressive Schottky junction reaction with the InAlAs and InGaAs materials, the lifetest at Tambient of 280°C projects the median-time-to-failure exceeding 1×106 hours at Tchannel of 125°C. This result indicates that the promising initial reliability performance was achieved on Pt-sunken gate InP HEMT MMICs on 4-inch InP substrates.

Wafer level bump technology that is compatible to III-V MMIC technology is reported. Two different wafer level bump technologies are presented in the paper. One is solder ball bump and the other is copper bump. Both are fully compatible with existing III-V MMIC backside manufacturing processes. Silicon nitride, deposited at room temperature, is used as solder mask and shows excellent solder blocking capability. UBM (Under-BumpMetallization) materials were specially selected for their solid diffusion barrier characteristics and strong adhesion between bump and MMIC backside metal pad. Bump planarity, shear strength and solderability are extensively characterized, and benchmarked with industry specifications

Northrop Grumman Aerospace Systems (NGAS) has developed a Wafer Scale Assembly (WSA) process that is compatible with Benzocyclobutene (BCB) processes. BCB is a common dielectric material used to construct multi-metal interconnects. BCB processes enable additional metallization layers to be available for circuits and signal routing. WSA is a technology that physically bonds two or more wafers together to create a hermetically packaged MMIC (Monolithic Microwave Integrated Circuit). Two additional BCB layers, translates to two additional metallizations added to each side of the WSA, increasing the number of interconnect layers on both sides. Combining BCB and WSA processes has several benefits, including but not limited to: added MMIC design flexibility, MMIC size reduction, and ability to create three-dimensional passive structures. In this paper, results from NGAS' development on the WSA-BCB integration are presented, and key process considerations are discussed.

A wafer-level-packaging technology was used to integrate the 0.1 mum AlSb/InAs HEMT low-noise amplifiers with power amplifiers, switches and phase shifters to form a compact tri-stack transmit/receive module for light-weight and ultralow-power applications. The high manufacturability of AlSb/InAs HEMT receivers operating at 0.9 mW was demonstrated on a tri-stack wafer. This demonstration of manufacturable tri-stack transmit/receive modules is essential for phased-array applications requiring light weight and ultralow power.

Wafer-scale-assembly (WSA) technology has been developed for compact and light-weight applications at the Northrop Grumman Corporation. To insure successful insertion of WSA hermetic MMICs for military and space applications, high-reliability demonstration is essential. In this study, we performed two-temperature lifetesting to evaluate the reliability performance of WSA hermetic GaAs HEMT MMICs. It was observed that gate sinking is still the primary degradation mechanism. In addition, finite-element thermal analysis was performed on the hermetic HEMT MMICs. The results showed an increase in channel temperature over similar non-hermetic GaAs HEMTs of approximately 8 °C. The median-time-to-failure (MTF) of approximately 5.6×106 hours at T channel of 125 °C was obtained based on reliability analysis with lower bound activation energy (Ea) of 1 eV. This promising result suggests that WSA technology could deliver reliable compact and light-weight HEMT MMICs for military and space applications.

We present on-wafer power measurements of 35 nm gate length InP HEMT amplifiers at 330 GHz. Various amplifiers are examined. The maximum output power of 1.78 mW is measured from a three stage amplifier. Additional output power may be possible but limited by our input power source level to saturate amplifiers. This result is the highest frequency on-wafer power measurement we are aware of reported to date, and demonstrates the technique we utilize to be a fast method of evaluating power performance of submillimeter wave amplifiers without the need to package devices.

Four types of gate metallization were investigated to evaluate the manufacturability of 0.1 mum AlSb/InAs HEMTs. It has been found that device performance strongly depends on the gate metallization. This information is essential for the manufacturability of 0.1 mum AlSb/InAs HEMTs for ultralow-power applications.

Maximizing In composition in the channel structures of high-electron-mobility transistors on InP is one important aspect of achieving devices capable of operating beyond 300 GHz. In this article, we compare dc and rf performance results from two variations of one such device design, incorporating a composite-channel structure comprised of InAs clad by InP-lattice-matched InGaAs. The only difference between these two variations is the thickness of the bottom InGaAs cladding layer. The thicker gave extremely high performance, with current-gain-cutoff frequency (f T ) exceeding 500 GHz, enabled by room-temperature channel-electron Hall mobility (mu e ) as high as 15,400 cm 2 /V/s and dc transconductance (g m ) exceeding 2700 mS/mm; but it also incurred significant impact ionization. The thinner incurred less of this short-channel effect and yet gave very high performance, with f T exceeding 440 GHz, enabled by mu e as high as 14,800 cm 2 /V/s and g m exceeding 2200 mS/mm, initially indicating that such a tradeoff might be the more overall beneficial. However, from a subsequent process iteration, in which the gate-recess etch was deepened for reduced short-channel effects, both of these same composite-channel design variations gave even better performance results. In that process iteration, the thicker variation not only achieved f T exceeding 500 GHz, but also achieved the recently-published new record maximum frequency of oscillation (f MAX ) exceeding 1 THz. Therefore, the thicker bottom InGaAs cladding layer has indeed proven to be the more optimal composite-channel design variation for performance beyond 300 GHz.

In this paper, an amplifier with a significant amount of gain is demonstrated at sub-millimeter wave frequencies (f > 300-GHz) for the first time. The three stage amplifier uses advanced InP HEMT transistors to realize 16-dB gain at 340-GHz and > 20 dB gain at 280-GHz. The amplifier demonstrates > 100 GHz of bandwidth with gain > 10 dB. This paper demonstrates that full WR-3 waveguide band (220-325 GHz) InP HEMT amplifiers are currently possible and that current device capabilities enable operation well into the sub-millimeter wave regime.

A new InP HEMT process has been developed with 35nm gate length and improved Ohmic contact. A gate-source capacitance of 0.4pF/mm is achieved with the reduced gate length, a 30% improvement over our baseline 70nm device. The contact resistance is successfully reduced to 0.07 with the newly designed contact layer combined with an alloyed Au/Ge/Ni/Au Ohmic metal. Good device characteristics has been demonstrated with a transconductance as high as 2 S/mm and a cutoff frequency fr of 420GHz. A single-stage common-source amplifier was fabricated with this new process. A peak gain of 5dB is measured at 265GHz. A MAG/MSG of 3dB at 300GHz was achieved, making the device suitable for applications at frequencies well into the millimeter-wave and even sub-millimeter-wave band.

In this letter, 254-, 314-, and 346-GHz fundamental oscillators are demonstrated. These are the highest frequency oscillators using three-terminal devices reported to date. The performance is enabled through a 35-nm InP HEMT process with maximum frequency of oscillation (f max ) of 600GHz. These first-pass designs use coplanar waveguide (CPW) technology and include on-chip resonator and output matching. The maximum available gain (MAG) of these devices has been measured to be ~9.6dB at 200GHz

We describe the measurement of the noise of a 270-GHz low noise amplifier using wafer-probe techniques. The measurement includes deembedding to the coplanar waveguide input of the chip. The noise was measured at a variety of bias conditions and found to be a minimum of 7.5 dB. The gain of the chip is measured to be 11.4 dB, consistent with s-parameter measurements of the same device. This is the highest frequency measurement of noise of a monolithic microwave integrated circuit amplifier and the only known on-wafer measurement of noise at this frequency. The, measurement demonstrates that wafer probe techniques developed at lower frequencies can be applied to circuits at submillimeter wavelengths.