The authors investigate the performance of a Metal–Insulator-Metal Field Controlled Tunneling Transistor (MIMT). In this structure, the flow of electrons between the source and the drain is due to a Fowler–Nordheim like tunneling mechanism through a dielectric whose potential barrier is modulated by the gate bias. This silicon-free device is immune to dopant fluctuations or band to band tunneling and its performance is solely limited by the tunneling mechanism. We have evaluated the theoretical device performance and proposed an analytical model capturing the underlying physics. The impact of material properties (dielectric permittivity, bandoffset) and geometrical parameters (gate oxide and tunneling oxide thickness, channel length) is discussed and guidelines for the fabrication of an optimized device are provided. We show that, with appropriate materials and architecture, a well tempered MIMT can demonstrate OFF current as low as 1nA/um and ON current on the order of 1mA/um for a voltage swing of 0.5V, making it an excellent candidate for ultra low power applications and thin film transistors. We also demonstrate that although its operation is based on tunneling, this device does not exhibit sub-60mV/dec subthreshold slope, but maintains nearly 60mV/dec between the OFF and ON-states.

This paper explore the potential of a Metal Insulator Metal gate controlled tunneling Transistor (MIMT) as a high performance device immune to band-to-band tunneling, GIDL, and stochastic channel doping fluctuations. A semi-analytical model was developed and used to guide device optimization. It is shown that the best performance is obtained by increasing the ratio between the permittivity of the gate oxide and the tunneling oxide as well as by integrating an ultra thin-body channel. The optimum channel length is around 8 nm. In a well tempered, optimized device, simulations show both an OFF current below 1 nA/¿m and an ON current above 1mA/ ¿m, by maintaining a steep subthreshold slope near 60mV/decade over a wide range of gate bias that is determined by the barrier height between the metal source and the dielectric channel.

To meet ITRS requirements, highly scaled MOSFETs will have to operate close to the quasi-ballistic regime and to exhibit enhanced injection velocity. Good performances may be achieved thanks to high transport materials such as germanium or III-V semiconductors. However their integration is still very challenging. Following a different approach, this paper proposes to examine how to improve the injection in conventional (100) silicon ultrathin-body (UTB) MOSFETs. A systematic investigation of the impact of the different usual technological parameters highlights that SG and DG exhibit comparable performances and that no improvement in the injection velocity is expected with the silicon thickness thinning down to 4 nm. Moreover the degradation of the injection velocity with the integration of high- dielectrics is shown. Finally, a significant improvement of the injection velocity due to a higher confinement in asymmetrical double gate MOSFET has been found. Similarly, it is shown that, single gate UTB MOSFETs with thin buried oxide (BOX) exhibit an enhanced injection velocity. In conclusion, only the reduction of the BOX thickness and the integration of strained channel have been found to be realistic and significant boosters of the injection velocity in silicon (100) MOSFETs. Prediction of the evolution of the injection velocity along the roadmap, using a pragmatic strategy of scaling, confirms that these two parameters will play a significant role in improving highly scaled (100) silicon devices performances.

In this work, an original and computationally efficient analytical model for quantization in FD-SG devices is proposed. It accounts for the coupling between the two interfaces, and leads to a proper modeling of energy levels, and consequently of ballistic and quasi ballistic currents. Suitable to model the impact of subband engineering on performances in the quasi ballistic regime of transport, such a model may also be used to extract from experiments the "degree of ballisticity" of real devices. It has been validated by comparison with Poisson Schrodinger (PS) simulations and experiments

This work presents a fully analytical model for the evaluation of quasi-ballistic transport in advanced bulk nMOS devices. Starting from the Lundstrom approach, an original analytical evaluation of energy levels advantageously replaces numerical time-consuming Poisson-Schrodinger simulations or usual analytical single subband approximations. This model allows an accurate estimation of quantum mechanical effects and their impact on quasi-ballistic performances. Based on an improved Airy method, it accounts for the non-linearity of the depletion potential, the wave function oxide penetration and a generalized concept of effective field. As it relies on subband structure, it can easily be extended to biaxially strained devices provided that the band modifications are known. Interest of strained channels is confirmed even on the base of ballistic or quasi-ballistic hypothesis. This model has been used for the evaluation of the "ballisticity" along the ITRS roadmap, showing for next generation devices a quasi-ballistic current slightly higher than that predicted with the usual drift diffusion and saturation velocity equations. However, as already reported, MOS devices still operate far from their ballistic limit down to HP45 nm node. (c) 2005 Elsevier Ltd. All rights reserved.

In this work, for the first time, are reported magnetoresistance (MR) mobility measurements performed on sub 0.1 mum Si MOSFETs. This method enables the carrier mobility to be measured from weak to strong inversion without knowing the device channel length. The MR mobility results are compared to effective mobility data obtained by standard parameter extraction and split C-V techniques. The MR data clearly indicate a significant decrease of the mobility with the gate length reduction. This behavior and the difference between MR and effective mobility values are discussed and interpreted by two-dimensional transport analysis.

This paper examines the performance of different NMOS devices (strained and unstrained bulk silicon, undoped single gate and double gate strained or unstrained SOI or SON devices) in the full ballistic regime of transport. The realism of this full ballistic transport assumption is also discussed, showing that even considering the most challenging structures, full ballistic transport will probably not be reached until channel length is lower than 10 nm.

We report on the high-field (up to 10T) magnetoresistance measurements performed on the short (down to 75-nm gate length) n-type Si metal-oxide-semiconductor field-effect transistors. The electron magnetoresistance mobility of these nanometer devices was determined for a wide range of the electron concentration (107–1013cm−2, i.e., from a weak to a strong inversion) and gate length (10μm–75nm). In the case of long samples, the magnetoresistance mobility was compared to the effective mobility obtained by the standard parameter extraction and the split C–V techniques. The results are discussed in terms of the scattering power-law two-dimensional transport analysis. The data clearly indicate a significant decrease of the mobility with the gate length reduction below 100nm.