It is well known that the large lattice mismatch (>14%) associated with CdTe/Si, CdTe/Ge, and CdTe/GaAs composite substrates, is a great contributor to large dislocation densities and other defects that limit the performance of HgCdTe-based infrared detectors. Though thermal expansion mismatch is another possible contributor to material defects, little work has been done towards documenting and understanding its effects in these systems. Here, we perform studies to determine the relative contributions of lattice and thermal mismatch to CdTe film characteristics, including dislocation density and residual stress. Unannealed and thermally cycled films are characterized using x-ray diffraction, defect decoration, and Nomarski and transmission electron microscopy. For CdTe/Si, the residual stress is consistently observed to be tensile, while for CdTe/Ge and CdTe/GaAs, a compressive residual film stress is measured. We show based on theoretically predicted stress levels that the experimental measurements imply the dominance of thermal mismatch in the residual stress characteristics.

We report on the significance of thermal expansion mismatch in the heteroepitaxial growth of CdTe on highly lattice-mismatched substrates. Such substrates including Si, Ge, or GaAs are desirable for CdTe buffer layer growth and subsequent deposition of HgCdTe infrared absorber layers. Besides lattice misfit, the thermal mismatch associated with these systems can produce additional strain and defects at low or elevated temperatures. However, little work has been done towards documenting and understanding these effects. Experimental evidence of thermal-expansion-dependent residual stress is presented for CdTe/Si(211), CdTe/Ge(211), and CdTe/GaAs(211) films based on X-ray diffraction studies. The experimental results are also compared with residual stress calculations based on known material properties. These results may play a vital role in the design and development of HgCdTe detectors for large-format, infrared focal plane arrays (FPA).

It has been reported that the basic electrical properties of n-type long wave length infrared (LWIR) HgCdTe grown on silicon, including the majority carrier mobility (μ e) and minority carrier lifetime (τ), are qualitatively comparable to those reported for LWIR HgCdTe grown on bulk CdZnTe by molecular beam epitaxy (MBE). Detailed measurements of the majority carrier mobility have revealed important differences between the values measured for HgCdTe grown on bulk CdZnTe and those measured for HgCdTe grown on buffered silicon substrates. The mobility of LWIR HgCdTe grown on buffered silicon by MBE is reported over a large temperature range and is analyzed in terms of standard electron scattering mechanisms. The role of dislocation scattering is addressed for high dislocation density HgCdTe grown on lattice-mismatched silicon. Differences between the low temperature mobility data of HgCdTe grown on bulk CdZnTe and HgCdTe grown on silicon are partially explained in terms of the dislocation scattering contribution to the total mobility.

The species and the nature of their chemical bonds at the surface of a hydrogen-terminated Si(211) wafer were characterized using temperature desorption spectroscopy, ion scattering spectroscopy, and electron spectroscopy. The surface region is dominated by monohydride species with dihydrides present in small amounts. Fluorine is distributed across the top layer as largely a physisorbed species to the Si substrate. Low-energy He+3 ions remove the H and F species with only minimal damage to the underlying region.

An empirical study is reported, wherein HgCdTe was deposited simultaneously on multiple CdZnTe substrates of different orientations by molecular beam epitaxy. These orientations included the following vicinal surfaces: (115)B, (113)B, (112)B, and (552)B. Additionally, growth on (111)B was explored. Growth conditions found to be nearly optimalfor the standard (112)B orientation were selected. Through a series of growth runs, substrate temperature was varied, and the physical properties of the resulting HgCdTe epilayers were measured. These measurements included Nomarski microscopy, infrared transmission, x-ray diffraction, and defect decoration etching. The properties of HgCdTe epilayers as a function of temperature were roughly similar for all vicinal surfaces. Namely, as the temperature increased, the dislocation density decreased. At some critical temperature, the density of void defects increased dramatically. This critical temperature varied with orientation, the (115)B exhibiting the lowest critical temperature and the (112)B and (552)B exhibiting the highest. The (115)B, (113)B, and (112)B orientations exhibited “needlelike” defects on the as-grown HgCdTe surface. The density of these defects decreased with increasing temperature. The (552)B surface exhibited no such defects and growth behavior nearly identical to the (112)B growthsurface.

A detailed analysis of the As-exposed Si (112) and subsequent Te exposure was performed. X-ray photoelectron spectroscopy shows that the Te- and As-exposed Si (112) surface had 70% As and 27% Te coverage, respectively. Direct surface coverage measurement with ion scattering spectroscopy (ISS) shows that the Si (111) surface is completely covered by As, and that of the Si (112) had about 78% and 20% coverage of As and Te, respectively. Finally, using ISS shadowing effects, it was found that the Te atoms were positioned mainly on the step edges.

We have fabricated a series of 256 pixel×256 pixel, 40 µm pitch LWIR focal plane arrays (FPAs) with HgCdTe grown on (211) silicon substrates using MBE grown CdTe and CdSeTe buffer layers. The detector arrays were fabricated using Rockwell Scientific’s double layer planar heterostructure (DLPH) diode architecture. The 78 K detector and focal plane array (FPA) performance are discussed in terms of quantum efficiency (QE), diode dark current and dark current operability. The FPA dark current and the tail in the FPA dark current operability histograms are discussed in terms of the HgCdTe epitaxial layer defect density and the dislocation density of the individual diode junctions. Individual diode zero bias impedance and reverse bias current-voltage (I-V) characteristics vs. temperature are discussed in terms of the dislocation density of the epitaxial layer, and the misfit stress in the epitaxial multilayer structure, and the thermal expansion mismatch in the composite substrate. The fundamental FPA performance limitations and possible FPA performance improvements are discussed in terms of basic device physics and material properties.

BxGa(1−x)As alloys have been grown by molecular beam epitaxy. Reducing growth temperature below 540°C and increasing the V/III flux ratio above 20 improved boron incorporation in the epitaxial layers while preserving crystal quality. Higher growth temperatures and lower V/III ratios lead to significant amounts of B incorporation on interstitial lattice sites. With optimized growth conditions, pseudomorphic BxGa(1−x)As films with x=0.078 have been grown with good crystal quality and no detectable interstitial B incorporation.