In this work, impurity ‘hot spot’ macro-defects—high impurity level macro-defect contaminates were examined. ‘Hot spots’ have very high localized concentrations of: K, Mg, Ni, Cr, Mn, Ca, Al, Na, Fe, and Cu. For example, these ‘hot spot’ macro-defects can have Cu concentrations > 1 × 1018 cm−3. Focused ion beam scanning transmission electron microscopy analysis of four ‘hot spots’ was performed. The origin of ‘hot spot’ defects is unresolved—however, our analysis has shown ‘hot spots’ can arise due to molecular beam epitaxy spit defects and CdZnTe substrate defects. The estimated ‘hot spot’ density is ∼ 30 cm−2. The presence of impurity ‘hot spot’ macro-defects in HgCdTe/CdZnTe is confirming evidence for the occurrence of L. Bubulac’s impurity ‘pipe’ mechanism.

State-of-the-art as-received (112)B CdZnTe substrates have been examined for surface impurity contamination and polishing residue. Two 4 cm × 4 cm and one 6 cm × 6 cm (112)B state-of-the-art as-received CdZnTe wafers were analyzed. A maximum surface impurity concentration of Al = 1.7 × 1015 atoms cm−2, Si = 3.7 × 1013 atoms cm−2, Cl = 3.12 × 1015 atoms cm−2, S = 1.7 × 1014 atoms cm−2, P = 1.1 × 1014 atoms cm−2, Fe = 1.0 × 1013 atoms cm−2, Br = 1.2 × 1014 atoms cm−2, and Cu = 4 × 1012 atoms cm−2 was observed on the as-received CdZnTe wafers. CdZnTe particulates and residual SiO2 polishing grit were observed on the surface of the as-received (112)B CdZnTe substrates. The polishing grit/CdZnTe particulate density on CdZnTe wafers was observed to vary across a 6 cm × 6 cm wafer from ∼4 × 107 cm−2 to 2.5 × 108 cm−2. The surface impurity and damage layer of the (112)B CdZnTe wafers dictate that a molecular beam epitaxy (MBE) preparation etch is required. The contamination for one 4 cm × 4 cm and one 6 cm × 6 cm CdZnTe wafer after a standard MBE Br:methanol preparation etch procedure was also analyzed. A maximum surface impurity concentration of Al = 2.4 × 1015 atoms cm−2, Si = 4.0 × 1013 atoms cm−2, Cl = 7.5 × 1013 atoms cm−2, S = 4.4 × 1013 atoms cm−2, P = 9.8 × 1013 atoms cm−2, Fe = 1.0 × 1013 atoms cm−2, Br = 2.9 × 1014 atoms cm−2, and Cu = 5.2 × 1012 atoms cm−2 was observed on the MBE preparation-etched CdZnTe wafers. The MBE preparation-etched surface contamination consists of Cd(Zn)Te particles/flakes. No residual SiO2 polishing grit was observed on the (112)B surface.

State-of-the-art as-received (112)B CdZnTe substrates were examined for surface impurity contamination, polishing damage, and tellurium precipitates/inclusions. A maximum surface impurity concentration of Al = 7.5 × 1014, Si = 3.7 × 1013, Cl = 3.12 × 1015, S = 1.7 × 1014, P = 7.1 × 1013, Fe = 1.0 × 1013, Br = 1.9 × 1012, and Cu = 4 × 1012 atoms cm−2 was observed on an as-received 6 × 6 cm wafer. As-received CdZnTe substrates have scratches and residual polishing grit on the (112)B surface. Polishing scratches are 0.3 nm in depth and 0.1 μm wide. The polishing grit density was observed to vary from wafer-to-wafer from ∼5 × 106 to 2 × 108 cm−2. Te precipitate/inclusion size and density was determined by near-infrared automated microscopy. A Te precipitate/inclusion diameter histogram was obtained for the near-surface (top ~140 μm) of a 6 × 6 cm substrate. The average areal Te precipitate/inclusion density was observed to be fairly uniform. However, there was a large density of Te precipitates/inclusions with a diameter significantly greater than the mean. Te precipitate/inclusion density >10 μm diameter = 2.8 × 103 cm−3. The large Te precipitates/inclusions are laterally non-uniformly distributed across the wafer.

State-of-the-art (112)B CdZnTe substrates were examined for near-surface tellurium precipitate-related defects. The Te precipitate density was observed to be fairly uniform throughout the bulk of the wafer, including the near-surface region. After a molecular beam epitaxy (MBE) preparation etch, exposed Te precipitates, small pits, and bumps on the (112)B surface of the CdZnTe wafer were observed. From near-infrared and dark field microscopy, the bumps and small pits on the CdZnTe surface are associated with strings of Te precipitates. Raised bumps are Te precipitates near the surface of the (112)B CdZnTe where the MBE preparation etch has not yet exposed the Te precipitate(s). An exposed Te precipitate sticking above the etched CdZnTe surface plane occurs when the MBE preparation etch rapidly undercuts a Te precipitate. Shallow surface pits are formed when the Te precipitate is completely undercut from the surrounding (112)B surface plane. The Te precipitate that was previously located at the center of the pit is liberated by the MBE preparation etch process.

HgCdTe is the material system of choice for many infrared sensing applications. Growth of this material can often be challenging. However, processing of this material system can be equally as challenging. Incorrect processing can cause shunting, surface inversion, or high surface recombination velocities that can be detrimental. In order to produce an effective device in HgCdTe, one needs to understand what happens to the HgCdTe surface. Factors like the chemical termination of the HgCdTe surface, surface roughness, and surface reconstruction after a process is performed can dramatically affect the performance of devices made with HgCdTe. We will review different surface characterization techniques and how these techniques can be used conventionally and unconventionally, and how different processes can affect the surfaces of HgCdTe and related compounds.

The crystalline structure and impurity profiles of HgCdTe/CdTe/alternate substrate (AS; Si and GaAs are possibilities) and CdTe/AS were analyzed by secondary-ion mass spectrometry, atomic force microscopy, etch pit density analysis, and scanning transmission electron microscopy. Impurities (Li, Na, and K) were shown to getter in as-grown CdTe/Si epilayers at in situ Te-stabilized thermal anneal (~500°C) interfaces. In HgCdTe/CdTe/Si epilayers, indium accumulation was observed at Te-stabilized thermal anneal interfaces. Impurity accumulation was measured at HgCdTe/CdTe and CdTe/ZnTe interfaces. Processing anneals were found to nearly eliminate the gettering effect at the in situ Te-stabilized thermal anneal interfaces. Impurities were found to redistribute to the front HgCdTe/CdTe/Si surface and p–n junction interfaces during annealing steps. We also investigated altering the in situ Te-stabilized thermal anneal process to enhance the gettering effect.

The surface kinetics of CdTe (211)B grown by molecular beam epitaxy (MBE) is investigated using spectroscopic ellipsometry (SE) during in situ cyclic annealing. A method of measuring sublimation rates from high-index surfaces without use of reflection high-energy electron diffraction is presented. The effect of Te 2 overpressure on the activation energy of sublimation for the CdTe (211)B surface is reported. The sensitivity of SE to surface temperature and film thickness was leveraged to monitor sublimation rates of CdTe stabilized by a Te 2 overpressure. The sublimation activation energy was found to increase from 0.45 eV to 2.94 eV under the Te 2 beam pressure regime investigated.

We describe the growth of CdTe (211)B by molecular beam epitaxy on large-area epiready GaAs (211)B substrates. Prior to CdTe growth, GaAs substrates were thermally cleaned under an As4 flux. Oxide desorption was verified by in situ spectroscopic ellipsometry (SE) and reflection high-energy electron diffraction. The use of in situ SE played a significant role in the study of CdTe-on-GaAs growth and annealing processes. An effective medium approximation (EMA) was used to model the overlayer thickness variation of CdTe epilayers throughout growth and in situ annealing cycles. A correlation between SE-derived EMA thickness values and surface defect formation mitigation is discussed. All annealed samples (11.5 μm to 13 μm thick) exhibited excellent crystalline quality with average double crystal rocking curve full-width at half-maximum (FWHM) values of ~60 arcsec.

Dislocations generated at the HgCdTe/CdTe(buffer layer) interface are demonstrated to play a significant role in influencing the crystalline characteristics of HgCdTe epilayers on alternate substrates (AS). A dislocation density >108 cm−2 is observed at the HgCdTe/CdTe interface. Networks of dislocations are generated at the HgCdTe/CdTe interface. The dislocation networks are observed to entangle. Significant dislocation reduction occurs within a few microns of the HgCdTe/CdTe interface. The reduction in dislocation density as a function of depth is enhanced by annealing. Etch pit density and x-ray diffraction full-width at half-maximum values increase as a function of the lattice mismatch between HgCdTe epilayer and the buffer layer/substrate. The experimental results suggest that only by reducing HgCdTe/CdTe lattice mismatch will the desired crystallinity be achieved for HgCdTe epilayers on AS.

Threading dislocations are a significant problem for heteroepitaxial growth of thin films on large lattice-mismatched substrates. In the case of HgCdTe thin films on Si, Ge, or GaAs, the molecular beam epitaxy (MBE) of 10-15-mu m-thick CdTe buffer layers has historically played a crucial role in reducing threading dislocation densities to current state-of-the-art levels. In this work, the authors investigate a localized substrate thinning approach and its overall effect on further reducing dislocation densities in the CdTe/Si heteroepitaxial system. In using substrates with regions thinned to thicknesses on the order of the CdTe buffer, the attempt is to reduce the dislocation image force acting from the interface toward the epilayer surface. The authors employ both wet-and dry-etching techniques to create locally back-thinned regions of Si(211) wafers. Localized rather than whole wafer thinning was necessary to maintain sufficient substrate thickness for handling. The opposite sides of the wafers were cleaned using standard techniques prior to CdTe MBE. Scanning electron microscopy and Fourier transform infrared spectroscopy were used to measure epilayer and substrate thicknesses. Using CdTe defect-decoration techniques, a decrease in threading dislocation density by up to 60% has been observed in regions for which the underlying Si substrate was thinned to 2 mu m. Results obtained for wet-etch and dry-etch back-thinning approaches suggest that the dislocation-reduction mechanism is not solely based on substrate-thickness induced image forces. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3547711]

Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order of 8 μm to 12 μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si may play a larger role.

HgCdTe heteroepitaxy on low-cost, large-lattice-mismatched substrates such as Si continue to be plagued by large threading dislocation densities that ultimately reduce the operability of the thermal imaging detector array. Molecular-beam epitaxy (MBE) of 10 μ m- to 15 μ m-thick CdTe buffer layers has played a crucial role in reducing dislocation densities to current state-of-the-art levels. Herein, we examine the possibility that growth on locally back-thinned substrates could prove advantageous in further reducing dislocation densities in the CdTe/Si heteroepitaxial system. Using defect decoration techniques, a decrease in dislocation (etch-pit) density of up to ~42% has been measured in CdTe regions where the underlying Si substrate was chemically back-thinned to ~20 μ m. A theoretical understanding is proposed, where a substrate-thickness-dependent dislocation image force is a likely cause for the experimentally observed reduction in threading dislocation density. These observations raise the prospect of combining localized substrate thinning with other techniques to further reduce dislocation densities to levels sought for HgCdTe/CdTe/Si and other large-lattice-mismatched systems.

The electrical performance of HgCdTe/Si photodiodes is shown not to have a direct relationship with the dislocation density as revealed by defect etching. This has led to an equivalent circuit model to explain the relationship of the dislocation density and the electrical test data. A new (112)B HgCdTe/CdTe/Si and CdTe/Si etch pit density (EPD) etch has been demonstrated. The new etch has been used to look for distinctive features which may be responsible for the poor electrical performance of individual diode pixels. The new etch chemistry also reduces the surface roughness of the etched epilayer and makes EPD determination less problematic. The new (to HgCdTe) technique of electrostatic force microscopy has also been used to analyze the electrical properties of dislocations.

X-ray diffraction full-width at half-maximum (XRD FWHM), reflection high-energy electron diffraction (RHEED), and atomic force microscopy (AFM) indicate a mosaic structure for molecular-beam epitaxy (MBE) (211)B CdTe/Si. AFM measurements indicate long, thin, small-angle-disoriented grains for CdTe/Si epilayers. These disoriented grains are ~1 μm in the [\( \overline{1} 11 \)] direction and are ~40 nm in the [\( 01\overline{1} \)] direction. The RHEED pattern in the [\( \overline{1} 11 \)] direction depicts nearly ideal single-crystal periodicity. The RHEED pattern in the [\( 01\overline{1} \)] direction is indicative of small-angle-disoriented crystalline grains. Scanning electron microscopy (SEM), AFM, and XRD measurements all indicate an approximate factor of 10 increase in the Everson etch pit density (EPD) over standard Nomarski microscopy Everson EPD determination.

The numerical fitnesses of species defined in the Bak-Sneppen model of self-organized criticality are interpreted as binary strings. This allows new species to be generated by mutation of survivors. It is shown that selection in Bak-Sneppen systems defined on both uniform and random lattices produces genotypes in conformity with the Eigen criterion for the accumulation of genetic information in macromolecular sequences.

Psoriatic spondyloarthropathy (PSA) can occasionally be complicated by AA amyloid, and renal amyloidosis should be suspected in patients with PSA who have unexplained proteinuria. The diagnosis of amyloidosis can be made either histologically or by radiolabelled serum amyloid P component (SAP) scintigraphy. Prognosis is determined by the extent of organ involvement and associated impairment of function, and by the degree of response of the underlying disease to anti-inflammatory therapy. A review of the literature identified less than a dozen cases of AA amyloidosis complicating PSA, and the outcome in most cases was poor. We report here the favourable clinical course of a middle-aged Caucasian male patient with severe PSA who developed renal AA amyloidosis, in whom treatment with oral chlorambucil led to stabilization of the amyloid deposits and resolution of the associated nephrotic syndrome. We review the diagnosis and treatment of AA amyloidosis, including the management of patients with underlying inflammatory spondyloarthropathies, and propose the possible role of a therapeutic trial of anti-tumour necrosis factor alpha in patients with amyloid complicating inflammatory rheumatic diseases.