An array of Single Photon Avalanche Diodes (SPAD), fabricated in a 180 nm CMOS technology featuring a high voltage (HV) option, has been investigated in terms of radiation tolerance, in view of the design of low material budget dual-tier detectors for charged particle tracking based on the coincidence of signals coming from pairs of vertically aligned pixels. Each pixel in the array includes both the processing electronics and the sensing element in a monolithic structure. The test vehicles were irradiated with 10 keV X-rays up to a dose of 1 Mrad (SiO2) and with neutrons up to a fluence of 10(11) n(eq) cm(-2). A selection of the characterization results are presented together with the main features of a new large scale SPAD array to be fabricated in a 150 nm CMOS technology and ready for vertical interconnection in a dual layer structure.

Single-photon avalanche diode (SPAD) arrays fabricated in a 180-nm CMOS technology with a high-voltage option have been exposed to calibrated neutron and X-ray sources to evaluate their radiation tolerance. The technology is being investigated in view of the design of low material budget detectors for charged particle tracking based on the coincidence of the signals coming from two or more overlapping layers of SPAD sensors. Each element in the array is a monolithic detector including the processing electronics together with the diode in the same substrate. Different sensor dimensions and structures have been implemented in the test chip to thoroughly explore the technology features. This paper will present and discuss the results from the characterization, in terms of dark count rate, of SPAD arrays irradiated with X-ray doses reaching 1 Mrad(SiO2) and with neutron fluences up to 10(11) 1-MeV neutron equivalent cm(-2).

In this paper we present a position-sensitive detector based on the vertical integration of pairs of aligned pixels operating in Geiger-mode regime and designed for charged particle detection. This novel device exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. This concept allows to have a reduced material budget and low power consumption in spite of a high granularity and fast timing response. A proof-of-principle prototype was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. This first demonstrator has been characterized and tested with a high energy particle beams at CERN SPS/PS facilities, in different configurations, featuring a reduction of the dark-count rate (DCR) at room temperature from similar to 100 kHz/mm(2) to about 24 Hz/mm(2) a particle detection efficiency limited only by the geometric factor. The device radiation tolerance has been investigated, via irradiation of single tiers with 10 keV X-rays up to a dose of 1 Mrad (SiO2) and with neutrons up to a fluence of 10(11) cm(-2). A second prototype, addressing the goal to improve the present fill-factor, has been designed, manufactured and approaches now the characterization phase. Potential applications of this sensor include high spatial resolution tracking in high-energy experiments, radiation monitoring in space and radiation imaging in nuclear medicine. A small hand-held demonstrator is under construction for radio-guided surgery.

In this paper, we present a two-layered silicon sensor working in Geiger-mode avalanche regime and designed for charged particle detection. Each position-sensitive element is comprised of two vertically aligned pixels, exploiting the coincidence between two simultaneous avalanche events to discriminate between particle triggers and dark counts. This approach potentially offers several advantages. First, a low material budget can be achieved thanks to the thinning of the detector down to a few tens of microns (e.g. 50 μm) as the avalanche starts in a shallow region just a few microns deep. Operation in a regime of quenched avalanche allows for an excellent timing resolution and provides an internal gain that makes a front-end amplification stage unnecessary, thus dramatically reducing the power consumption. Fine detector segmentation is possible as the (horizontal) inter-pixel cross-talk in the detection plane can be reduced to a comfortable level while the vertical cross-talk is totally eliminated using a metal light-shield layer. The detector is also insensitive to background light. A number of applications could benefit from a detector with these characteristics, including particle tracking and vertex reconstruction in particle physics experiments at accelerators and in space, as well as ionizing radiation imaging in nuclear medicine and life-sciences.

The main purpose of this work is to investigate the characteristics of a 180nm CMOS technology with high voltage (HV) option in view of the fabrication of a dual-tier, low material budget sensor for charged particle detection. For this purpose, an array of avalanche pixels has been designed. The array includes sensors with a pitch of 50μmx100μm, different sizes (20μmx20μm, 30μmx30μm and 40μmx36μm) and different process layers. Active and passive quenching techniques to suppress the avalanche have been implemented in the front-end electronics, which is integrated in the same substrate as the sensor. The paper presents the results from the characterization of the test chip in terms of breakdown voltage and dark count rate (DCR).