The load/store pipe for a low-power 1-GHz embedded processor is described. For area savings and logic complexity reduction, the load/store pipe is clocked at twice the frequency of the processor core. It can sustain two load or store operations per core clock cycle with zero load to use issue latency. The address generation unit for one of the two load/store pipes takes advantage of the common addressing mode in MIPS 64 ISA to generate the address within a core clock phase. Phase borrowing is employed in the translation lookaside buffer (TLB) design to enable a lookup process within a core clock phase. The data cache design enables the activation of a minimum number of data bank arrays for power savings. Small-swing differential buses are used for multiple address and data buses for improved signal transmission latency. The quadrature clocks used to derive the 2× clock are generated with a novel 4-to-1 divider and distributed with matched paths, all to reduce the duty cycle variation of the 2× clock phase. The design has been implemented in a 0.13-μm CMOS process.

The load/store pipe in an embedded processor is clocked at 2/spl times/ the processor clock frequency. It sustains two load or store operations per core clock cycle with zero load-to-use issue latency. The design is implemented in 0.13/spl mu/m 7M CMOS process and dissipates between 650 and 1090mW for core clock frequencies between 600MHz and 1GHz.

The load/store pipe for a low-power 1-GHz embedded processor is described. For area savings and logic complexity reduction, the load/store pipe is clocked at twice the frequency of the processor core. It can sustain two load or store operations per core clock cycle with zero load to use issue latency. The address generation unit for one of the two load/store pipes takes advantage of the common addressing mode in MIPS 64 ISA to generate the address within a core clock phase. Phase borrowing is employed in the translation lookaside buffer (TLB) design to enable a lookup process within a core clock phase. The data cache design enables the activation of a minimum number of data bank arrays for power savings. Small-swing differential buses are used for multiple address and data buses for improved signal transmission latency. The quadrature clocks used to derive the 2 x clock are generated with a novel 4-to-1 divider and distributed with matched paths, all to reduce the duty cycle variation of the 2 x clock phase. The design has been implemented in a 0.13-mum CMOS process.

The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.

This custom CPU derived from the StrongARM/sup TM/ 110 is capable of more than 2 billion 16 b operations per second (2 BOPs). Starting with the original design, an attached media processor (AMP) is integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements are made to the CPU and cache subsystem and the chip is reduced from 0.35 /spl mu/m to 0.28 /spl mu/m technology. The chip includes 3.3M transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0 V internal, 3.3 V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip. For battery powered applications, Vdd is reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudo-static and supports clock stop and IDDQ testing.

This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply. The chip may also be operated at 215 MHz with a 2.0 V internal supply dissipating 1.1 W. The external interface always runs at 3.3 V. The die contains 2.1 M transistors and measures 7.8/spl times/6.4 mm/sup 2/. It is fabricated in 2.0 V 0.35 /spl mu/m 3-layer metal CMOS and packaged in a 144-pin thin quad flat pack. Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board. The chip is pseudo-static and the internal clocks may be stopped in either phase to minimize power consumption.