Abstract This paper covers methods used to isolate single leaky junctions in a test structure designed for Flash memory technology development. It may be possible to isolate this failure through micro probing or a combination of electrical testing and physical structure modification by FIB, but at the expense of spending numerous days. The paper shows that a combination of emission microscopy (EMMI), electron beam induced current (EBIC) characterization and a SEM nano-probing can drastically simplify the fault isolation process. Results of nano-probing are also shown to prove the level of leakage detected in the faulty junction. A combination of EMMI and EBIC characterization was able to pinpoint the problematic junction from approximately 2500 junctions in the structure. Furthermore, the nano-probing IV characterization proved the identified junction to be indeed high in leakage current, providing further confidence for physical failure analysis.

Extended abstract of a paper presented at Microscopy and Microanalysis 2009 in Richmond, Virginia, USA, July 26 – July 30, 2009

Extended abstract of a paper presented at Microscopy and Microanalysis 2009 in Richmond, Virginia, USA, July 26 – July 30, 2009

The dielectric and structural properties of LaAlO3 make it an attractive epitaxial gate oxide for nanometer-scale field effect transistors. However, the growth of epitaxial LaAlO3 directly on Si has not been possible to date. In order to achieve LaAlO3 epitaxy, we use a SrTiO3 template layer whose thickness minimizes elastic strain and atomic-level buckling at the interface. We find that LaAlO3 grown on this template layer is crystalline and initially strained, but relaxes to its bulk lattice constant within 7 unit cells. Cross-sectional transmission electron microscopy and inelastic electron tunneling spectroscopy studies of the LaAlO3/SrTiO3/Si structure show no evidence of an amorphous SiO2 layer. Capacitance-voltage measurements on thin films of epitaxial LaAlO3/SrTiO3/Si with LaAlO3 thicknesses between 13 and 110 nm show a dielectric constant for the LaAlO3 layer of 24, the same value as for the bulk. After a post-deposition low temperature anneal, these oxide heterostructures show no Fermi level pinning and an interface state density of ∼8×1010 cm−2 eV−1.

Extended abstract of a paper presented at Microscopy and Microanalysis 2007 in Ft. Lauderdale, Florida, USA, August 5 – August 9, 2007

We report on magnetic field and temperature-dependent measurements of the anisotropic magnetoresistance (AMR) in epitaxial La1−xSrxMnO3 (LSMO) thin films. While in 3d ferromagnetic alloys increasing the magnetization, either by reducing the temperature or increasing the magnetic field, increases the AMR, we find that in LSMO films the AMR dependence on magnetization displays nonmonotonic behavior which becomes particularly pronounced in lightly doped compounds. We believe that this behavior is related to the inhomogeneity exhibited by these materials.

Journal Article ctfExplorer: Interactive Software for 1d and 2d Calculation and Visualization Of TEM Phase Contrast Transfer Function Get access Max V Sidorov Max V Sidorov Materials Technology Development, Advanced Micro Devices, Sunnyvale, CA 94088-3453 Search for other works by this author on: Oxford Academic Google Scholar Microscopy and Microanalysis, Volume 8, Issue S02, 1 August 2002, Pages 1572–1573, https://doi.org/10.1017/S1431927602104442 Published: 01 August 2002

We report on performance and scalability for strained Si CMOS devices with Lgate down to 25nm, 1.2nm nitrided oxide and NiSi. Good control of short channel effects was achieved. NiSi was found to be superior to CoSi2 for strained Si devices. Electron mobility enhancement resulted in significant Idsat improvement for long channel NMOS. Due to high doping and significant DC self-heating, the Idsat improvement diminishes with gate length scaling. However, more improvements were observed for Idlin and at a high temperature. Consistently, more improvement in ring oscillator speed was observed for a low Vdd at a high temperature. Introduction Transistor scaling has been the primary factor driving CMOS performance improvement for more than 30 years. Approaching the fundamental limits of transistor scaling drives the industry and research community to actively search for alternative materials and new device architectures to boost the performance. Strained Si epitaxially grown on relaxed SiGe increases the electron and hole mobility and can be used to enhance FET performance [1-3]. Recently, sub-100nm strained Si CMOS devices with performance enhancement have been demonstrated [4]. In this late-news paper, we report performance of 25nm strained Si CMOS devices and address scalability issues for the strained Si technology. Device Design and Fabrication In addition to conventional scaling challenges, key issues for strained Si devices include Si/SiGe band-offset induced Vt shift, differential diffusion of dopants in SiGe, limited strained Si thickness, strain relaxation, and Ge diffusion at high temperatures. In this work, Vt/halo implants and doping activation anneal were optimized to compensate the band-offset induced Vt lowing and control the enhanced diffusion of As in SiGe for NMOS. Strained-Si consumption was minimized by optimizing the clean and oxidation steps. Thermal budgets were also reduced by optimizing oxidation and anneal steps. Thermal budget control is important not only for strain considerations, but also for Ge diffusion control. Substrates were strained-Si on Si0.8Ge0.2, with a CMP step introduced before device layer growth to reduce the surface roughness [5]. Fig.1 shows a strained Si MOSFET with a 25nm Lgate patterned by 193nm lithography. Fig.2 shows a composition image by STEM for the same FET, showing NiSi and strained Si layers. The strained Si layer can be more clearly seen in a high resolution STEM image (Fig.3). To control short channel effects, a 1.2nm nitrided gate oxide is used. A HRTEM cross-section of the gate oxide is shown in Fig.4. Fig.5 and 6 show the transistor’s IV characteristics. In this experiment, the drive currents of ~615uA/um (NMOS) and ~317uA/um (PMOS) are measured at Vdd of 0.9V, with Ioff <100nA/um for both devices. The transistors are the smallest strained Si transistors reported to date. With thin gate oxide and optimized Vt/halo implants, good control of short channel effects was achieved for both Pand NFETs, despite enhanced As diffusion in NMOS. Fig.7 shows good threshold voltage roll-off characteristics down to 25nm gate length. Silicide was found to be a key module for realization of the strained Si technology. SiGe in strained Si substrate inhibits Co silicide transition to the low resistivity phase, resulting in a high silicide sheet resistance with a large variation. Ni reacts with both strained Si and SiGe and forms low sheet resistance silicide and germanosilicide [6]. Fig.8 shows the sheet resistance and standard deviation for Ni and Co silicides in strained Si devices with typical silicidation processes. Performance and Scalability Measured electron and hole mobility characteristics are shown in Fig.9. Compared to the unstrained device, strained Si NMOS displays significant mobility enhancements over a wide Eeff range. No significant hole mobility improvement was observed for the strained Si structure studied. The electron mobility enhancement results in significant Idsat improvement (>50%) for long channel NMOS (Fig.10). However, the Idsat improvement diminishes as the gate length is scaled down. In the present study, there is almost no Idsat improvement for 25nm devices at room temperature. The reduction in Idsat enhancement is believed to be due to high channel doping and severe self-heating in short channel devices. The high channel doping in short channel devices caused by halo implants degrades mobility. Low thermal conductivity of SiGe and high drive current of short channel NMOS cause severe self-heating during the DC measurements [4]. However, this is not expected to have a serious impact on transistor performance for digital applications, since the thermal time constant for degradation (greater than 100ns) is much larger than the typical transistor on time [7]. At a high temperature, influences of self-heating and Coulomb scattering decreased and greater improvement was achieved. Despite similar Lgate and temperature dependences, more Idlin improvement was observed due to an increasing influence of mobility and decreasing self-heating effects (Fig.11). Consistently, greater improvement in ring oscillator speed was observed for a low Vdd at a high temperature (Fig.12). Summary Strained Si CMOS devices down to 25nm Lgate were fabricated with 1.2nm gate oxide and NiSi. Electron mobility enhancement resulted in significant Idsat improvement for long channel NMOS. Idsat improvement at DC decreases as gate length is scaled down. Further device/process optimization may offset this trend. More improvements were observed for drive current at low Vds and at a high operation temperature. More improvement in ring oscillator speed was also observed for a low Vdd at a high temperature. Acknowledgement: The authors like to thank David Kyser, Craig Sander of AMD and Mark Wolf of AmberWave for managerial support. References [1] K.Rim, et al., IEDM Tech. Dig., p.707, 1998 [2] R.Tezuka, et al., VLSI Tech. Dig., p.96, 2002 [3] K.Rim, et al., VLSI Tech. Dig., p.59, 2001 [4] K.Rim, et al., VLSI Tech. Dig., p.98, 2002 [5] M.Currie et al., J. Vac. Sci. Tech. 19(6), p.2268, 2001 [6] H.Zhao, et al., J. Appl. Phys. 92 (1), p.214, 2002 [7] K.Jenkins, et al., IEEE EDL 16(4), p.145, 1995

A conceptual design of toroidal and poloidal field systems for the ARIES-RS reactor study is presented in this paper. Means of designing the toroidal and poloidal field system for minimized size and cost, optimized structure and increased access for maintenance are presented in the paper. Supports of the out-of-plane TF loads that do not interfere with maintenance operation have been designed. Structural analyses of several cases that have the common feature of avoiding material in between the outer legs of the TF coil are presented in this paper. The implications on the structural amount of material required are investigated. Methods of handling failure conditions in the toroidal field coil due to unbalanced currents are studied. Optimization of the conductor in the poloidal and toroidal field systems is carried out. Implications of the use of very fine superconducting strands for conductor stability and minimization of co-wound normal-conducting material are evaluated. Implications of novel schemes for magnet protection such as internal dump, are described.

The ARIES-RS tokamak is a conceptual, D–T-burning 1000 MWe power plant. As with earlier ARIES design studies, the final design of ARIES-RS was obtained in a self-consistent manner using the best available physics and engineering models. Detailed analyses of individual systems together with system interfaces and interactions were incorporated into the ARIES systems code in order to assure self-consistency and to optimize towards the lowest cost system. The ARIES-RS design operates with a reversed-shear plasma and employs a moderate aspect ratio (A=4.0). The plasma current is relatively low (Ip=11.32 MA) and bootstrap current fraction is high (fBC=0.88). Consequently, the auxiliary power required for RF current drive is relatively low (∼80 MW). At the same time, the average toroidal beta is high (β=5%), providing power densities near practical engineering limits (the peak neutron wall loading is 5.7 MW m−2). The toroidal-field (TF) coil system is designed with relatively `conventional' materials (Nb3Sn and NbTi conductor with 316SS structures), and is operated at a design limit of ∼16 T at the coil in order to optimize the design point. The ARIES-RS design uses a self-cooled lithium blanket with vanadium alloy as the structural material. The V-alloy has low activation, low afterheat, high temperature capability and can handle high heat flux. A self-cooled liquid lithium blanket is simple, and with the development of an insulating coating, has low operating pressure. Also, this blanket gives excellent neutronics performance. Detailed analysis has been performed to minimize the cost and maximize the performance of the blanket and shield. One of the distinctive features of this design is the integration of the first wall, blanket, parts of the shield, divertor and stability shells into an integral unit within each sector. The maintenance scheme consists of horizontal removal of entire sectors. Prior to the initiation of the ARIES-RS study, a set of top-level requirements and goals for fusion demonstration and commercial power plants was evolved in collaboration with representatives from US electric utilities and from industry. The degree to which ARIES-RS reached these requirements and goals and the necessary trade-offs are described and the high-leverage areas and key R&D items are presented.

Helical magnets have been manufactured of both high Tc and low Tc materials. The helical magnets are manufactured from solid hollow cylinders. A helix is machined in the cylinders, resulting in one-layer solenoids. In this paper, results of a BSCCO 2212 helical magnet are discussed. The magnet has been tested in fields up to 15 T. Stability, quench protection, and critical parameters have been determined. Results of local heating of the magnet, and the resulting quench propagation, have been studied. A distributed method of quench protection has been tested. The results may be used for quench protection of large high-Tc magnets. The details of the testing are described.

The high current required to drive the toroidal field coil of Low Aspect Ratio reactor-size devices (due to the single turn design) results in difficult choices for the electrical bus. In this paper, the implications of both superconducting and resistive busbar are investigated. Special attention is given to the possibility of using a high-TC busbar.

A new type of magnet design is proposed, where the conductor is composed of conducting pebbles in a low-melting temperature conducting matrix. The magnet should have high radiation tolerance. At the end-of-life of the conductor, the pebbles can be circulated out of the magnet after the conducting matrix is molten. Ap plication of this approach to the centerpost in the Low Aspect Ratio Device are discussed.

Apparatus for the investigation of low and high-T/sub c/ superconducting spirals has been designed and built. The device is capable of measuring the characteristic of superconducting spirals. The superconducting spirals are on a normally conducting substrate. The normally conducting substrate serves as a shunt between the superconducting turns, serving as a distributed quench protection resistor. Samples with both high and low electrical resistance substrates have been tested on this apparatus. Preliminary results of the tests of both high-T/sub c/ (Bi-Sr-Ca-Cu-O) and low-T/sub c/ (Nb-Ti) thick-film spirals have been investigated. Current distribution in films during quench has been studied experimentally. Generation of normal zone and hysteresis current-voltage characteristics have been discovered in high-T/sub c/ superconducting spirals on silver plate. It is shown that frequency of generation of normal zone depends at under certain conditions (transient current, magnetic field, temperature and resistivity of substrate). The results are being analyzed with models.< >