The damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL, can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.

In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

A novel metallization scheme was developed to enable advanced BEOL interconnect scaling. The proposed approach adopts electroless Co to selectively grow Co in vias, followed by conventional Cu metallization for the trench. We have demonstrated the feasibility of this approach through the process integration of electroless Co via pre-fill on a two metal layer interconnect test structure. A detailed discussion on the yield improvement, parametric data, and reliability will be presented in this paper.

The highest performing microprocessors, memory devices, and other computer chips require the most advanced technologies. Improving performance of the device is much more than just shrinking the dimensions: it requires novel materials innovations. BEOL interconnect performance has been improved by the migration from aluminum-based interconnects and oxide interlayer dielectrics to copper interconnects in a dual inlaid architecture and with low-k dielectrics. Inlaid Cu lines offer higher conductivity, improved electromigration resistance, and a reduced cost of manufacturing; however, as feature sizes continue to scale, metals to replace Cu are being researched. In this presentation, the novel materials innovations being researched to enhance performance, improve reliability, and enable technology scaling for the integrated circuit (IC) industry will be highlighted. A historical perspective on BEOL interconnect challenges and innovations to reduce capacitance and improve conductivity will be shown. Future BEOL interconnect metallizations will be critically reviewed.

Metal-Insulator-Semiconductor (MIS) Schottky diodes were fabricated to study Fermi level unpinning by use of a thin TiO x insulator. For Ti-TiO x -n-Si junctions, the Schottky barrier height (SBH) was pinned due to O diffusion from TiO x into Ti during thermal anneals, as observed from XPS depth profiles. A thin AlO x barrier inserted between the Ti and the TiO x prevented O diffusion from TiO x into Ti, allowing SBH unpinning to be maintained after 450 °C anneals.

In this paper we will report the results of TiN metal gate recession using a dilute mixture of sulfuric acid, hydrogen peroxide and hydrofluoric acid known by the trade name DSP+

As advanced silicon semiconductor devices are transitioning from planar to 3D structures, new materials and processes are needed to control the device characteristics. Atomic layer deposition (ALD) of HfxAlyCz films using hafnium chloride and trimethylaluminum precursors was combined with postdeposition anneals and ALD liners to control the device characteristics in high-k metal-gate devices. Combinatorial process methods and technologies were employed for rapid electrical and materials characterization of various materials stacks. The effective work function in metal–oxide–semiconductor capacitor devices with the HfxAlyCz layer coupled with an ALD HfO2 dielectric was quantified to be mid-gap at ∼4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material that allows for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit devices.

Environmentally assisted debonding at Cu/barrier interfaces is reported for oxidizing and reducing environments. Both moist and dry oxidizing environments are considered, and the effects of different oxidizing species and their chemical activity on the rate of debonding of a Cu/SiN interface is quantified. The type of oxidizing species is shown to play a critical role in the kinetics of environmentally assisted debonding. Additionally, the effect of varying the activity and temperature of reducing hydrogen environments is investigated. The mechanisms responsible for environmentally assisted debonding of Cu/SiN and Cu/SiCN interfaces are elucidated using an atomistic bond rupture model. An activation energy for debonding of Cu/SiCN interfaces in a hydrogen environment is calculated. Finally, a connection between environmentally assisted debonding and the time-dependent dielectric breakdown properties of Cu interconnects is proposed.