Charge storage properties of 20–30 nm gate oxides implanted with Si+ ions are investigated using MOS capacitors, single transistor structures and a non-volatile memory. The observed programming window can reach several volts for programming with electric fields of about 4–7 MV/cm. The structures exhibit good retention (250 °C, 280 h) and the endurance (>106 w/e-cycles) considerably exceeds the typical values of present EEPROM technologies. The capability of Si implanted SiO2 films as gate dielectrics for a real non-volatile memory is demonstrated for the first time by a 256 K-non-volatile static random access memory showing a programming window of larger than 1 V.

The concept of a nanocrystal memory [1,2] has several attractive features. First, it overcomes limitations of current (Flash)-EEPROM technologies: higher endurance and lower voltages become possible enabling further scaling and memories of higher density. Second, the retention characteristics can be possibly tailored from DRAM-like to EEPROM-like memories by adjusting the cluster size and their distance to the Si/SiO2 interface. Third, the simple transistor structure and the full CMOS compatible process integration ability makes the nanocrystal memory to be an ideal candidate for an embedded memory designed for system-on-chip applications.

Electrical properties of 20–30 nm gate oxides implanted with Si+ ions are investigated using MOS capacitors and transistors. The observed programming window can reach several volts and the devices exhibit good retention behavior. A first 256 k – nvSRAM is demonstrated showing a programming window >1 V for write pulses of 12 V/8 ms.

MOSFETs with gate oxides containing nanoclusters (Si,Ge) fabricated with different techniques (implantation, LPCVD, sputtering) are a very promising approach for future memories. This contribution reports on results obtained on Si- or Ge-implanted MOS capacitors and transistors. By varying the implantation and annealing parameters the Si or Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate-SiO/sub 2/ containing Si- or Ge-nanoclusters are investigated in detail with emphasis on its feasibility for embedded memories for system on chip applications.

MOSFETs with gateoxides containing nanoclusters (Si, Ge, Sn, Sb) fabricated with different techniques (implantation, LPCVD, sputtering) are very promising for future memories. This contribution reports on results obtained on Ge-implanted MOS capacitors. By varying the implantation and annealing parameters, the Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate SiO2 containing Ge nanoclusters are investigated in detail with emphasis on its feasibility for memory applications.

Nanocluster memories are promising for future non-volatile memory applications. In this work thin SiO 2 films were implanted with Ge + and Si + and annealed subsequently. Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements. Positive voltage pulses lead to a positive flatband voltage shift of the C-V curve. Detrap-ping by applying negative voltage pulses leads to a negative shift. The achieved programming window using 6 V / 100 ms pulses for Ge based structures is higher than that for Si (2.0 V vs. 0.2 V). However the retention times for Si based memories are longer. For dedicated process parameters microstructural investigations (RBS, XTEM) of Ge + implanted SiO 2 layers showed two bands of clusters, one near the interface SiO 2 /Si and one in the center of the SiO 2 layer.

Nanocluster memories are promising for future non-volatile memory applications. In this work thin SiO2 films were implanted with Ge+ and Si+ and annealed subsequently. Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements. Positive voltage pulses lead to a positive flatband voltage shift of the C-V curve. Detrapping by applying negative voltage pulses leads to a negative shift. The achieved programming window using 6 V / 100 ms pulses for Ge based structures is higher than that for Si (2.0 V vs. 0.2 V). However the retention times for Si based memories are longer. For dedicated process parameters microstructural investigations (RBS, XTEM) of Ge+ implanted SiO2 layers showed two bands of clusters, one near the interface SiO2/Si and one in the center of the SiO2 layer.