Zinc Oxide (ZnO) Thin-Film Transistors (TFTs) using Aluminum (Al) and Aluminum-doped zinc Oxide (AZO) as Source-Drain (S-D) contacts are reported. The fabrication process was carried out using five photolithography steps with a maximum processing temperature of 100 °C, which makes the process compatible with flexible/transparent applications. The AZO and ZnO films were deposited using Pulsed Laser Deposition (PLD). Aluminum was deposited using ebeam. The devices showed mobilities >10 cm2/V-s, threshold voltage in the range of 7 V and On/Off current ratios >105. The resistance analysis showed that AZO is a better contact with lower contact resistance as identified in the TFTs. The AZO and ZnO stacks characterized by UV-V shows an optical transmission >80 %.

Developments of flexible detection arrays suggest that portable robust detectors are indeed possible. A large area flexible array promises a large capture cross section in a light weight rugged format suitable for deployment at ports of entry. The approach for this detector uses a high neutron-capture cross-section layer, such as 10 B, which captures incident thermal neutrons, and emits energetic ionizing charged particles. These ionizing particles are sensed using an integrated diode. The resulting charge is then amplified via a low-noise thin film transistor amplifier. We present a low-noise optimized active pixel sensor (APS) design which can be implemented in either a low temperature InGaZnO or an a-Si:H thin film transistor (TFT) process compatible with plastic substrates. Here, we also present a detectable alpha particle response with our dual stage APS design in combination with an externally connected commercial PIN diode. Furthermore, we discuss detector and array modeling which will further aid in future designs.

In this letter, we demonstrate the feasibility of building thin-film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) operational amplifiers (op-amps) at low temperature (180°C) for large-area sensor applications. The classic two-stage Miller-compensated CMOS design is built using a-Si:H and pentacene TFTs. In addition, we have studied the impact of electrical stress-induced aging of TFTs on op-amp performance using two different kinds of biasing circuits.

NBTI of the HfSiOx/TiN gate stack is investigated as a function of the dielectric thickness. It is shown that as the thickness of the HfSiOx layer is reduced below 20Å, the NBTI mechanism approaches the mechanism that induces H-reaction diffusion. Conversely, for thicker HfSiOx dielectrics, a combination of H-reaction-diffusion and charge detrapping from the bulk HfSiOx contribute to NBTI.