Increasing demand on high-speed mobile access requires a spectrum-efficient wireless connectivity platform. With dense modulation and MIMO techniques, 802.11ac WLAN has been widely deployed as a viable solution. The emerging 802.11ax standard promises increased network capacity and higher data-rates. As 802.11ac/ax imposes stringent linearity requirements on power amplifiers (PAs), a high peak-to-average power ratio, operation at large power back-off, and reduced PAE are unavoidable. As a result, III-V processes [1] have dominated the development of high-output-power (POUT) WLAN PAs. To replace them with lower cost Si-based PAs, several linearization schemes [2], [3] have been proposed, such as digital pre-distortion (DPD) and a spatial power combining, at the cost of increased complexity in the digital domain. In [4], a 2nd-harmonic short is used for linear Class-AB PAs, but an inductor on the supply lane occupies Si area and causes ohmic losses, degrading POUT and PAE. SiGe HBTs [5] are suitable for WLAN PAs due to their high power density, ruggedness, and CMOS compatibility. However, as current gain ($\beta $) drops with junction-temperature (TJ) rise, this distorts PA linearity and power gain.

A multimode 5-6 GHz SiGe BiCMOS PA IC that powers the emerging Wireless LAN applications is presented. The design can be realized in a 1.35 × 0.7 active area as a standalone power amplifier (PA) or the transmit (Tx) chain of a Front-end IC. The design features multiple modes with low DEVM supporting 1024 QAM data rates and >20 dB accurate power controls. The linearity is well scaled with supply voltage from 2.8V to 5.5 V and insensitive to modulation bandwidths and duty cycles. With a 5 V supply, the PA has 32 dB gain and meets -41 dB DEVM for 1024 QAM, up to 20 dBm Pout and -35 dB DEVM for 256 QAM 802.11ac up to 21 dBm Pout. The design has also support a low power mode having 3 dB less linear power, with reduced current. With DPD, the low linearity mode can achieve similar linear power as the high linearity mode with 40 mA current reduction. The diverse features of the PA IC simplify front-end circuit designs of emerging high throughput radio standards.

A multimode 4.9–5.9 GHz ultra-linear single chip front-end integrated circuit (FEIC) for 802.11ac and emerging multi-gigabit per second (Gbps) wireless local area network (WLAN) applications is presented. The design is based on SiGe BiCMOS and realized in a 2.0 x 2.0 x 0.5 mm3 package. The FEIC design consists of both transmit (Tx) and receive (Rx) chains, which integrates a single-pole double-throw (SPDT) Tx/Rx CMOS switch, a SiGe power amplifier (PA), and a SiGe low noise amplifier (LNA) with a CMOS bypass attenuator. The SiGe PA in the transmit chain integrates input and output matching networks, harmonic filters, out-of-band rejection filters, supply voltage regulator and multi-mode bias circuits, temperature and voltage compensated power detector with on-chip directional coupler, and CMOS-compatible enable circuitry. The PA is controlled by the on-chip temperature and voltage compensated bias controller. With a 5 V supply, the transmit chain features 31 dB gain and excellent linearity. The transmit chain can deliver 19 dBm output power with current consumption 220 mA meeting below -40 dB Dynamic Mode Error Vector Magnitude (DEVM) for 1024 QAM signals and 20 dBm with current consumption 250 mA meeting below -35 dB DEVM for 256 QAM signals. The feature of ultra-low DEVM enables the emerging 1024-QAM applications. The harmonics emissions of the transmit chain can achieve below -50 dBm/MHz, greatly exceeding FCC out-of-band emission requirements. In addition, the linearity of the transmit chain output power is well scaled with the supply voltage from 3.0 V to 5.5V and insensitive to signal modulation bandwidths as well as duty cycles. The low linearity mode features 50 mA lower current consumption comparing to the high linearity mode. With the use of digital pre-distortion (DPD), it can achieve the similar linear power with 50 mA current reduction. The integrated log detector with an on-chip directional coupler ensures the accurate power control over 24 dB with less than 0.5 dB power control inaccuracy under VSWR 3:1 mismatch, which significantly increases the dynamic range and accurate power control for the transmit path. The Rx chain features noise figure (NF) below 2.5 dB with 15 dB gain and the current consumption of 8 mA as well as 8 dBm IIP3. The receive chain also integrates an 8 dB bypass attenuator having 25 dBm IIP3 with 3uA current consumption, which can prevent the WLAN radio from saturation under high field strength illuminations. All these unique features provide a turn-key solution for the single band or dual-band 802.11ac radio front-end circuits and emerging multiple gigabits per second high linearity WLAN radio designs. Figure 1

A highly integrated 4.9-5.9 GHz single chip front-end IC (FEIC) is presented, which is based on SiGe BiCMOS, realized in a 1.6 mm2 chip area and in an ultra-compact 1.7 × 2.0 × 0.33 mm3 package. The Tx chain has >30 dB gain and meets -40 dB DEVM up to Pout of 15 dBm and -35 dB DEVM up to Pout of 17 dBm with a 3.3 V supply, insensitive to modulation bandwidths and duty cycle. The ultra-low back-off DEVM enables the emerging 1024-QAM applications. The integrated log detector enhances the dynamic range for the transmit power control. The Rx chain features <;2.8 dB NF and 15 dB gain with 3 dBm IIP3 and 10 dB bypass attenuator with 23 dBm IIP3. All the unique features enhance the front-end circuit designs of complex radios based on the 802.11ac standard.

A compact high linearity 4.9-5.9 GHz T/R FEM is presented, which consists of a SiGe BiCMOS PA and a SOI switched LNA realized in an ultra-compact 2.3 × 2.3 × 0.33 mm3 QFN package. The Tx chain has > 30 dB gain and meets -35 dB DEVM up to 17 dBm at 3.3 V and 20 dBm at 5V, insensitive to modulation bandwidths and transmission data length up to 4 mS. With digital pre-distortion (DPD), the PA can be down-biased to save 30 mA while maintaining its linearity. The Rx chain features <;2.5 dB NF and 12 dB gain with 4 dBm IIP3 and 8 dB bypass attenuator with 29 dBm IIP3. All the unique features enhance the front-end circuit designs of complex 802.11ac radios.

This chapter focuses on some of the radiofrequency (RF) and millimetre-wave (MMW) applications that a through-silicon via (TSV) technology can enable. We will first discuss a grounded TSV application for a RF wireless communication power amplifier that is in mass production. A grounded TSV is essentially a metal connection that takes the active device interconnect to a package ground without needing to go through wire bond. A tungsten-filled grounded TSV delivers over 75% reduction in inductance compared to a traditional wire bond, thus enabling higher frequency applications in silicon technology. Such a grounded TSV is seamlessly integrated into a 350-nm SiGe BiCMOS.Next we show feasibility on insulated TSV that is utilised in a digital technology for high speed I/O functions, such as, in an advanced microprocessor. The insulated TSV sits in a 3D-IC carrier silicon chip that is made compatible with standard 90-nm high performance CMOS processing. The TSV arrays are designed to provide minimal resistance and inductance with excellent yield and breakdown voltage characteristics. A commercial application of this concept is for the emerging 100-Gb Ethernet that requires almost 1 Tbps data transmission between ICs.This concept of insulated via in a 3D-IC environment is then extended to a 130-nm MMW SiGe BiCMOS technology. We introduce the concept of a Wilkinson power divider that can be utilised in a 60-GHz phased array radar system.

A highly integrated SiGe BiCMOS power amplifier for dual-band WLAN applications is presented. The PA has 2 and 3 stages of amplification for the ‘b/g’ and ‘a’ band, respectively, and integrates the input/output matching network, out-of-band rejection filter, power detector, and bias control. The die area is 1.7 × 1.6 mm2. The b/g amplifier achieves 28 dB gain with 19.5 dBm output power at 3% EVM and 185mA and harmonics of <−45dBm/Mhz. The a-band amplifier achieves 30 dB gain with 3% EVM at 19.0 dBm output with 220mA of current and harmonics < −50 dBm/MHz. The reported PA linearity, out-of-band rejection, and integration level exceeds previously reported WLAN dual-band SiGe PA designs.

An innovative Silicon-On-Insulator (SOI) SP4T T/R switch is presented. The SP4T switch consists of 2 receive paths with an integrated dual-band LNA and bypass attenuators along with 2 high linearity matched transmit paths. Tx paths feature 0.1 dB compression to 34 dBm input power and 0.5–0.8 dB insertion loss from 1 to 6 GHz with ≫ 20 dB return loss and ≫ 25 dB isolation. Receive paths feature 16 dB gain with 2.3 dB NF for 2.4–2.5 GHz and 14 dB gain with 2.4–2.6 dB NF for 4.9–5.9 GHz. The band selectivity exceeds 40 dB. Cascading with a dual-band WLAN PA, a complex dual-band WLAN/MIMO front-end module (FEM) can be easily constructed with low assembly complexity and post PA losses resulting in dual-band transmit linearity ≫18 dBm with EVM ≪ 3% and ≪ −50 dBm/MHz harmonic emissions within a 4 × 5 mm QFN package.

a novel dual-band DPDT T/R switchplexer is presented. The switchplexer has a low-loss Tx path and a fully integrated Rx diplexer using die area ≪ 0.15 mm2. Tx path has 0.1 dB compression at ≫ 31.8 dBm with 1 dB insertion loss (IL) and ≫ 20 dB isolation from 2.4 to 5.9 GHz. The switch features ultra low EVM distortion up to 26 dBm power input with harmonic emission ≪ −50 dBm. Rx path has switch and diplexer losses of 2.0 dB and 2.2 dB IL for ‘b/g’ and ‘a’ bands, respectively. The band selectivity is ≫ 15 dB. These unique features simplify the dual-band front-end by reducing the total number of ICs to 2 or 3 in a simple low cost package.

A highly integrated 5 x 5 x 0.9 mm(3) dual-band Wireless LAN front-end module (FEM) is presented. The FEM features 29 dB gain and 19 dBm at 54Mbps with EVM < 3% and 180 mA for 2.4 to 2.5 GHz. For 4.9 to 5.9 GHz transmission, the FEM delivers 25 dB gain and 17 dBm at 54Mbps with EVM < 3% and 195 mA. The FEM's receive chains can be realized either with LAN having > 11.4 dB gain LNA gain with NF < 2.5 dB for the low band and < 2.8 dB for the high band or with used a RX diplexer with < 1 insertion loss. The FEM significantly simplifies 802.11 a/b/g radio designs and provides an effective building block for multi-channel 802.11n radios designs.

A power amplifier chipset for GSM and WCDMA mobile handset PAs has been designed and fabricated in the IBM Silicon Germanium BiCMOS 5AM process. This 3-chip set offers competitive performance and reliability for integrated GSM/DCS-PCS/WCDMA applications. The constant envelope (GSM and DCS-PCS) power amplifier designs are optimized for efficiency under pulsed GMSK conditions, achieving 55% and 45% PAE at 900 and 1880 MHz, respectively, at 3.4 V. The linear (WCDMA) amplifier performance has been optimized for continuous HPSK operation with - 36dBc ACPR maximum with up to 27 dBm output power. This family of PAs relies on two biasing architectures to address pulsed and linear operation by effectively utilizing the broad library of devices available in the BiCMOS process. Power device design and thermal conductivity of the silicon substrate are such that reliable operating temperatures during multi-slot GSM and WCDMA operation are assured. ICs are assembled in low-cost, 50-ohm matched modules or 4mm leadless (QFN) packages.