This paper presents a fully integrated Ku-band coupled Voltage Controlled Oscillator (VCO) with very low phase noise performances, implemented in the QUBiC4X 0.25 μm SiGe:C BiCMOS process of NXP semiconductors. The originality of this design consists in using two coupled VCOs with a new bias circuit to improve the pushing and the phase noise. Under 5 V supply voltage and a maximum total power dissipation of 231.5 mW, the proposed VCO features a phase noise of -121.4 dBc/Hz at 1 MHz frequency offset. The VCO is tuned from 13.53 GHz to 14.79 GHz with a tuning voltage varying from 1 V to 4.5 V and occupies 0.84×1.85 mm 2 .
This paper presents three different technology modules, integrated into a 0.13-μm SiGe BiCMOS process; namely RF-MEMS switch, microfluidics and heterogeneous integration technologies. The RF-MEMS switch module is optimized for mm-wave applications and offers superior performance figures at D-band with a wafer level encapsulated packaging option. The microfluidics module which is embedded by bonding three different wafers, provides a unique platform of fluid-electronic interaction with possibility of optical observation. Finally, the FOWLP option provides the heterogeneous integration of a single or multi chips in a single package. The BiCMOS process together with the integration of all these modules offers a technology platform to follow the More-than-Moore path for multi-functional and smart systems.
A frequency, bias and output power independent linearization technique for reducing the non-linear base-collector capacitance related distortion is proposed. Based on Volterra series analysis, the optimum base-collector capacitance for linear device operation is determined while respecting physical constrains. It is shown that by modifying the extrinsic base-collector region for an otherwise uncompromised device, the Cbc linearity compensation can be included within the transistor design itself. The practicality of this implementation is demonstrated by considering the doping profile accuracy requirements for achieving a significant OIP3 improvement of at least 5dB.
In this paper we study and analyze the existing techniques in literature to extract the self-heating thermal resistance from the measured DC electrical behaviour of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) focusing their dependence on device junction temperature and propose a simple extraction technique that shows superior accuracy than the existing extraction methodologies. Our approach is scalable and validated with model card simulations across different emitter geometries for a wide temperature range. We also present the applicability of our approach on measured data of a SiGe HBT fabricated in STMicroelectronics B55 process.
A novel balanced reflect-type vector modulator topology is presented. The use of only four 90° hybrid couplers allows a much-reduced area, competitive with active solutions, while keeping all benefits of the passive topology. A test circuit was developed using a 0.25 μm SiGe BiCMOS technology. The K-band vector modulator occupies 353 × 435 μm and measurements showed a very well centered and uniformly distributed constellation. The maximum gain at 20.35 GHz equals -9.61 dB and return losses are above 10 dB. The use as a 16-QAM modulator is evaluated and in a 20% relative bandwidth, the circuit demonstrated amplitude and phase RMS errors of 0.7 dB and 4°, respectively. Between the 16 configurations, the worst input referred 1dB compression point (P in,1dB ) obtained is 5.8 dBm with relative phase variations smaller than 3.73°.
A monolithically integrated C-band receiver is used to demonstrate the potential of an advanced photonic BiCMOS process. We show that the particular SiGe HBTs integrated in this process strongly improve the receiver's frequency response, BER and noise behavior, compared to the same circuit fabricated in a previous process generation featuring slower transistors.
The operation of SiGe HBTs at cryogenic temperatures is investigated experimentally and theoretically. It is demonstrated that the collector current at cryogenic temperatures is caused by electron tunneling through the base. The temperature dependence of the transistor characteristics reveals a transition from conventional thermally activated transport at room temperature to tunneling dominated transport at cryogenic temperatures. Experimental results are presented for HBTs with a peak current gain of 8000 at 300 K and 45000 at 10 K.
This paper presents a 28-32 GHz transceiver chip architecture in SiGe BiCMOS to meet the requirements of 5G phased-array communication links. An asymmetric design is employed for the transmit and receive paths to deliver an output P1dB of 8 dBm in TX mode and to achieve an input P1dB of 0 dBm in RX mode. The chip can operate with an external LO at 10-16 GHz and 20-28 GHz with the use of an on-chip doubler option. All switches on RF, LO and IF paths are implemented using SiGe HBTs for low loss and wideband operation. An on-chip elliptic filter is implemented in the TX path to reject the upconverted image and LO leakage to meet spectral mask requirements. The chip was tested in the TX mode with an 802.11ad MCS-10 waveform and achieves 3.9% EVM at 3 Gbps physical rate.
Achieving a wideband, efficient, scalable and low-cost interface between IC and antennas is critical for mm-wave transceivers in silicon. This paper presents an antenna-IC co-integration approach to achieve dual-polarization transmission and reception using on-chip dual-pol feeds that aperture-couple through a slot in the on-chip ground to a patch antenna on the back side of the IC. The proposed wafer-scale compatible approach is demonstrated with a 60 GHz prototype that includes a dual-pol 60 GHz receiver frontend (RXFE) implemented in the TowerJazz SBC18H3 SiGe technology. The RXFE includes a cross-pol cancellation path (with variable gain and phase shift) to cancel cross-polarization leakage signal to enable concurrent dual-pol operation. The antenna co-integration approach achieves ~50% and 2.7 dBi simulated efficiency and gain, with measured dual-pol reception and ~30 dB cross-pol leakage cancellation. Extensive ground-plane reuse leads to the 60 GHz dual-pol RXFE and antenna feed and slot structures occupying 1.8 mm × 1.8 mm of die area.
This paper presents a 20.35 GHz low power, high gain, low-noise amplifier (LNA) with a 30 GHz band-stop filter embedded in the matching network. Designed in a 0.25 μm SiGe:C BiCMOS technology, it meets the specifications imposed by a full-duplex K/Ka-band shared aperture active phased-array antennas for satellite communications. The LNA exhibits a measured gain of 32.8 dB at 20.35 GHz and a 3 dB bandwidth of 2.25 GHz. The measured IIP3, IP 1dB , and OP 1dB are -21.2, -34.3 and -2.5 dBm, respectively. Including the losses due to the band-stop filter and the bondwire interconnects between chip and board, it achieves 3.5 dB NF at the center frequency. Among published K-band counterparts in Silicon technologies, the LNA has the highest gain and the best figure of merit, considering noise, gain, and linearity. It consumes only 7 mW, with a chip area of 407 × 287 μm 2 .
This paper deals with the reduction of the process thermal budget in a 55-nm BiCMOS technology for improving SiGe HBTs transit frequency, fT. Since MOSFETs are directly impacted by this modification, process adjustments are implemented to recover performances and parametric yield. Spike annealing temperature reduction, thermal re-oxidation replacement and Dynamic Surface Annealing implementation are discussed. A 355 GHz Ft/ FMax HBT compatible with current 55-nm MOSFET models is demonstrated.
A novel training technique for digital predistortion (DPD) systems is presented. Previous techniques rely on the time-domain (TD) difference between the ideal transmitter input and the distorted amplifier output as an error metric. This work presents DPD training based solely on frequency-domain signal-to-distortion-ratio (SDR) information. The only a priori information required is the spectral occupancy of the desired signal. The approach is applied to a broadband SiGe BiCMOS power amplifier, including measured results.
This paper presents a 2:1 Analog Multiplexer (AMUX) in a SiGe-HBT technology. The AMUX is used for time interleaving operation of two digital-to-analog converters (DACs) and therefore extends both the sampling rate and the bandwidth compared to a single DAC. The linear AMUX signal path allows for generation of broadband signals with higher order modulation schemes which is essential for raising data rates in optical communication networks. The AMUX provides a differential peak-to-peak output voltage of up to 1 V with linear gain. A signal path 3-dB bandwidth exceeding 6 7 GHz has been measured. The clock path exhibits a 3-dB bandwidth of 6 0 GHz. S-parameter measurements are presented. Measured PAM4 eye diagrams at 5 6 GS/s from the time interleaving operation of two DACs are reported.
A differential linear TIA implemented in a 130 nm SiGe: C BiCMOS technology with ft/fmax/BVcEo of 300 GHz/500 GHz/1.7 V is presented. It features a bandwidth of 60 GHz, 62.5 dBO differential transimpedance gain and 5.46 pA/√Hz averaged input-referred current noise density, while dissipating 85 mW of DC power. The measured THD is better than 3% for ~ 450 mVppd output swing and input current of 400 μApp. Clear NRZ eye diagrams up to 56 Gb/s, as well as PAM-4 eye diagrams up to 30 GBd are also reported. To the author's best knowledge, this design exhibits record low-noise performance among > 50 Gb/s-class silicon-based broadband TIAs towards 100/400 Gb/s optical links.
A multimode 5-6 GHz SiGe BiCMOS PA IC that powers the emerging Wireless LAN applications is presented. The design can be realized in a 1.35 × 0.7 active area as a standalone power amplifier (PA) or the transmit (Tx) chain of a Front-end IC. The design features multiple modes with low DEVM supporting 1024 QAM data rates and >20 dB accurate power controls. The linearity is well scaled with supply voltage from 2.8V to 5.5 V and insensitive to modulation bandwidths and duty cycles. With a 5 V supply, the PA has 32 dB gain and meets -41 dB DEVM for 1024 QAM, up to 20 dBm Pout and -35 dB DEVM for 256 QAM 802.11ac up to 21 dBm Pout. The design has also support a low power mode having 3 dB less linear power, with reduced current. With DPD, the low linearity mode can achieve similar linear power as the high linearity mode with 40 mA current reduction. The diverse features of the PA IC simplify front-end circuit designs of emerging high throughput radio standards.
It is envisioned that future 5G wireless links will extensively employ multiple mm-Wave spectra (e.g., 28GHz, 37GHz, 39GHz, and 70GHz). A major bottom neck for silicon-based mm-Wave electronics lies in the generation of mm-Wave signals with high energy efficiency, high linearity, and large modulation bandwidth, all of which are indispensable to support Gbit/s complex modulations with large peak-to-average-power ratio (PAPR) in 5G systems. In this paper, we focus on two technical aspects that recently attract increasing attention and may together address these challenges. We will first present Doherty power amplifier (PA) architecture that offers large back-off efficiency enhancement, linear operation, and low overhead on signal processing. A recent multi-band (28/37/39GHz) mm-Wave Doherty PA in a 130nm SiGe process will be presented as a design example. Next, we will present a new concept of antenna-electronics co-design at mm-Wave. A new “Multi-Feed Antenna” (MFA) is recently proposed and demonstrated by the authors to achieve direct on-antenna low-loss power combining of multiple mm-Wave PAs. A 60GHz all-silicon transmitter design employs on-chip MFA to combine power from 16 PAs and achieves state-of-the-art total radiated output power per transmitter element.
In this paper, we discuss architectures and integrated circuits for efficient, reconfigurable and compact millimeter-wave beamforming in silicon. First, we present techniques to improve peak and back-off power-added efficiency ( PAE) of SiGe power amplifiers, demonstrated with a 28-GHz harmonic-tuned amplifier (+15.5 dBm output 1-dB compression point, 35% peak PAE, 11.5% PAE at 6-dB back-off) and a 60-GHz Doherty amplifier (+17.1 dBm output 1-dB compression point, 23.7% peak PAE, 13% PAE at 6-dB back-off). Second, we present a dual-vector Doherty beamformer architecture which allows reconfiguration between an efficient Doherty mode (+16.7 dBm output 1-dB compression point and 7% PAE at 6-dB back-off) and a linear class-AB mode (+13 dBm output 1-dB compression point and 4.5% PAE at 6-dB back-off), demonstrated in SiGe at 60 GHz. Finally, we present a compact architecture for beamformers which employs dual-vector scaling functions within each element and then global combining and interpolation. This is demonstrated with a 28-GHz dual-vector receiver array in SiGe which requires only 0.3 mm(2) for each receiver front-end.
An 8:1 multiplexer with a power output stage (PMUX) in SiGe BiCMOS technology for directly driving a plasmonic Mach-Zehnder modulator (MZM) with a 2 V pp differential voltage swing at a data rate of 100Gbit/s is presented. The PMUX is intended to be monolithically integrated with an ultrashort MZM on a single chip in a novel silicon photonic process. Through this integration, the bandwidth and output voltage swing could be improved compared to an external MZM load that requires far end termination. Furthermore, the direct driving by the PMUX eliminates the traditional driver amplifier, whereby power can be saved and the signal quality can be improved. Electrical measurements of the MUX show clear eye openings at 100Gbit/s up to a 2.0 V pp differential output voltage swing at an external 50 Ω oscilloscope load. The inherent high-speed capability of the PMUX is demonstrated at the speed limit of the available measurement equipment at 140Gbit/s, where the PMUX still achieves 1.2 Vpp differential voltage swing, which is a record for SiGe bipolar technology.
Radio-Frequency (RF) losses on High-Resistivity Silicon (HRS) substrates were studied for several different surface passivation layers comprising thin-films of SiC, SiN and SiO 2 In many combinations, losses from conductive surface channels were reduced and increasing the number of interfaces between thin-films was found to be beneficial. In some cases the surface losses were completely eliminated. For example, with plasma-enhanced chemical-vapor deposition (PECVD) α-SiC layers up to a few tens of nm thick and exposed to nitridation or SiN growth at 850°C to form a SiC:N interface layer, values for the total losses of 1.6 dB/cm were achieved. Analysis of these layers was performed by using temperature dependent measurements of the RF losses on Coplanar Waveguides (CPWs), the capacitance-voltage characteristics and the sheet resistance along the Si surface. The overall results can be explained by assuming that the thin-films are so defected that they allow vertical current paths to highly-resistive interface layers where both fixed and mobile charge can be stored.
this paper presents a Verilog-A compact model adaptation for a High Voltage SiGe HBT in a DTI on SOI process incorporating characteristic changes observed from a Field Effect Electrode. The output characteristics of the Bipolar are controlled, or 'tuned', by what is effectively an additional terminal. The model proposed is based on MEXTRAM and includes a new terminal node. The main additional effects are captured through the use of empirical formulae, while maintaining the bulk of the original code. The model is validated against DC and AC results from on-wafer Si test structures.
