Implantable medical devices (IMDs) have been used to manage a broad range of diseases and ailments. They are convenient for patients due to their small sizes, unobtrusiveness and portability using wireless monitors or controllers. However, the wireless communication between these devices and their controllers often lacks security features or mechanisms. This lack of security makes the use of these devices a fertile ground for passive and active attacks. Unlike other cyber attacks which target victims' information or property, attacks on medical devices can threaten a victim's life. Currently, there are very few efficient solutions to these attacks which balance security, reliability, and power consumption. Therefore, in this work, we propose a robust approach for guarding against existing and potential communication-based attacks on IMDs while keeping the added hardware and power consumption low. In addition, we introduce a secure and efficient protocol for authorizing third-party medical teams to access the IMDs in the case of an emergency. (C) 2018 Elsevier Ltd. All rights reserved.

It has been publicly known that keyboards and mice, either wired or wireless, can be potentially attacked by eavesdropping or hijacking. Although there are many secure keyboards and some secure mice in the market, there are still vulnerabilities under different types of Man-In-The-Middle (MITM) attacks such as hijack or replay. Usually these attacks are low cost and easy to implement, but so far there have not been any effective solutions to them. This paper proposes a protection scheme against the existing and potential MITM attacks to wireless keyboards and mice while keeping a low overhead in hardware and energy consumption, which is critical to battery powered devices. This lightweight scheme can also be applied to other wireless devices sensitive to battery life such as implantable medical devices. Index terms — keyboard, mouse, security, eavesdropping, hijack, tampering, replay, man-in-the-middle, encryption, authentication, AES, AMD, error control codes.

Most cache designs support single or double bit-level error detection and correction in cache lines. However, a single error may distort a whole byte or even more, resulting in much higher decoding complexity than that of bit-level distortions. Thereby this paper proposes a new group testing based error correcting code (GTB code) for byte-level error locating and correcting which provides much stronger protection for memories. This new class of non-binary GTB codes is generated from binary superimposed codes. Since it is encoded and decoded by binary matrices, no complicated Galois Field computations in GF(Q) such as multiplications and inversions are involved. Comparing with popular non-binary error correcting codes (ECC) such as Hamming, Reed-Solomon and interleaved codes, the GTB codes achieves up to 42% reduction of the decoding complexity (hardware cost × latency) for single-byte error correction, and up to 98% reduction for double-byte error correction. Moreover, given the length of codewords (e.g. 512 bits for cache lines), as the size of each Q-ary digit (byte) increases, the saving increases.

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under he primary entry in the Author Index.

In this paper, we consider the problem of constructing minimal cycle-breaking connectivity preserving sets of turns for graphs that model communication networks, as a method to prevent deadlocks. Cycle-breaking provides for deadlock-free wormhole routing constrained by turns prohibited at some nodes. We present lower and upper bounds for minimal cardinalities of cycle-breaking connectivity preserving sets for several classes of graphs such as homogeneous meshes, \mbi p-ary \mbi n-cubes, cube-connected cycles, hexagonal and honeycomb meshes, tori, etc.

Shamir's secret sharing scheme is an effective way to distribute secret to a group of shareholders. But this scheme is vulnerable to cheaters and attackers and thus how to protect the system from cheating and attacks is a big problem. In this paper, we proposed to use robust codes and algebraic manipulation detection (AMD) codes to protect the secret sharing module. Simulation and synthesis results show that the proposed architecture can improve the security level significantly even under strong cheating and attack models with some extra area and timing overheads.

Memories used in cryptographic devices are vulnerable to fault injection attacks. To mitigate the danger of these attacks, error control codes are often used in memories to detect maliciously injected faults. Most of codes proposed for memories in cryptographic devices are error detecting codes with small Hamming distances that cannot be used for error correction. While being able to provide sufficient protection against fault injection attacks, these codes cannot provide a satisfactory reliability under the presence of random errors. In this paper we present reliable and secure memory architectures based on two nonlinear error correcting codes. The presented coding technique can be used for detection of fault injection attacks as well as for correction of random errors. The construction and the error correction procedures for the code will be described. The error handling methodology used to distinguish between random errors and maliciously injected faults will be discussed.

The reliability and security of memories are crucial considerations in the modern digital system design. Traditional codes usually concentrate on detecting and correcting errors of certain types, e.g. errors with small multiplicities or byte errors, and cannot detect or correct unanticipated errors. In this paper we present a reliable and secure memory architecture based on robust Algebraic Manipulation Correction codes. These codes can provide a guaranteed error detection probability and can correct any error regardless of its multiplicity as long as the error stays for several consecutive clock cycles. The construction and the error correction procedure for the code will be described. The probability that an error can be successfully detected and/or corrected and the hardware overhead of the memory architecture based on these codes will be estimated.

Multi-level cell (MLC) nand flash memories are popular storage media because of their power efficiency and large storage density. Conventional reliable MLC nand flash memories based on BCH codes or Reed-Solomon (RS) codes have a large number of undetectable and miscorrected errors. Moreover, standard decoders for BCH and RS codes cannot be easily modified to correct errors beyond their error correcting capability t=[(d-1/2)], where d is the Hamming distance of the code. In this paper, we propose two general constructions of nonlinear multi-error correcting codes based on concatenations or generalized from Vasil'ev codes. The proposed constructions can generate nonlinear bit-error correcting or digit-error correcting codes with very few or even no errors undetected or miscorrected for all codewords. Moreover, codes generated by the generalized Vasil'ev construction can correct some errors with multiplicities larger than t without any extra overhead in area, latency, and power consumption compared to schemes where only errors with multiplicity up to t are corrected. The design of reliable MLC nand flash architectures can be based on the proposed nonlinear multi-error correcting codes. The reliability, area overhead and the penalty in latency and power consumption of the architectures based on the proposed codes are compared to architectures based on BCH codes and RS codes. The results show that using the proposed nonlinear error correcting codes for the protection of MLC nand flash memories can reduce the number of errors undetected or miscorrected for all codewords to be almost 0 at the cost of less than 20% increase in power and area compared to architectures based on BCH codes and RS codes.

Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive adversaries with limited attack capabilities. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200%-400%). In this paper we propose a novel error detection technique based on the random selection of linear arithmetic codes and explore the use of this technique for the protection of the multiplier, which is a basic block in many public-key cryptographic devices. The error detection technique does not imply any limitations on the types of errors at the output of the device, e.g., the multiplicity of the error does not have to be small. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (at most 50% area overhead for the protection of multipliers) due to the fact that no nonlinear operations are needed for the encoder and decoder.

Cryptographic devices are vulnerable to fault injection attacks. All previous countermeasures against fault injection attacks based on error detecting codes assume that the attacker cannot simultaneously control the fault-free outputs of a device-under-attack and error patterns. For advanced attackers who are able to control both of the above two aspects, traditional protections can be easily compromised. In this paper, we propose optimal algebraic manipulation detection (AMD) codes based on the nonlinear encoding functions and the random number generators. The proposed codes can provide a guaranteed high error detecting probability even if the attacker can fully control the fault-free outputs of a device-under-attack as well as the error patterns. As a case study, we present the protection architectures based on AMD codes for multipliers in Galois fields used for the elliptic curve cryptography. The results show that the proposed architecture can provide a very low error masking probability at the cost of a reasonable area overhead. The protected multiplier has no latency penalty when the predictor is pipelined.

The security of the cryptographic device may be compromised if the FSM of the system is not properly protected [1]. FSM protection architectures based on linear codes cannot provide a guaranteed level of protection under the assumption of a strong attack model. In this paper, we propose secure FSM architectures based on the idea of randomly selecting one code from a set of codes for each encoding and decoding operation. Assuming that the attacker is able to inject specific error patterns, randomly selecting one code from L codes as described in the paper can reduce the chance for the attacker to conduct a successful attack by a factor of L. The proposed techniques can achieve much higher security level than architectures based on linear codes with reasonable hardware overhead for cryptography applications (120% – 130% for the protection of the FSM for the Montgomery ladder algorithm). The security level of the proposed architectures can be increased by increasing L and the number of information bits k of the codes.

The problem of preventing deadlocks and livelocks in computer communication networks, in particular, those with wormhole routing, is considered. The method to prevent deadlocks is to prohibit certain turns (i.e., the use of certain pairs of connected edges) in the routing process, in such a way that eliminates all cycles in the graph. We propose a new algorithm that constructs a minimal (irreducible) set of turns that breaks all cycles and preserves connectivity of the graph. The algorithm is tree-free and is considerably simpler than earlier cycle-breaking algorithms. We prove its properties and present lower and upper bounds for minimum cardinalities of cycle-breaking connectivity preserving sets for graphs of general topology as well as for planar graphs. In particular, the algorithm guarantees that not more than 1/3 of all turns in the network become prohibited. We also present experimental results on the fraction of prohibited turns, the distance dilation, as well as on the message delivery times and saturation loads for the proposed algorithm in comparison with known tree-based algorithms. The proposed algorithm outperforms substantially the tree-based algorithms in all characteristics considered.

In this paper we propose memory protection architectures based on nonlinear single-error-correcting, double-error-detecting (SEC-DED) codes. Linear SEC-DED codes widely used for design of reliable memories cannot detect and can miscorrect lots of errors with large Hamming weights. This may be a serious disadvantage for many modern technologies when error distributions are hard to estimate and multi-bit errors are highly probable. The proposed protection architectures have fewer undetectable errors and fewer errors that are miscorrected by all codewords than architectures based on linear codes with the same dimension at the cost of a small increase in the latency penalty, the area overhead and the power consumption. The nonlinear SEC-DED codes are generalized from the existing perfect nonlinear codes (Vasil’ev codes, Probl Kibern 8:375–378, 1962; Phelps codes, SIAM J Algebr Discrete Methods 4:398–403, 1983; and the codes based on one switching constructions, Etzion and Vardy, IEEE Trans Inf Theory 40:754–763, 1994). We present the error correcting algorithms, investigate and compare the error detection and correction capabilities of the proposed nonlinear SEC-DED codes to linear extended Hamming codes and show that replacing linear extended Hamming codes by the proposed nonlinear SEC-DED codes results in a drastic improvement in the reliability of the memory systems in the case of repeating errors or high multi-bit error rate. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.

We report a systematic study of effects of temperature and current density on magnetization reversal of thin Ni films and arrays of nanoscopic Co clusters embedded in Pt matrix, in search of mechanisms stimulating magnetization reversal which are not related to spin polarization or to Joule heating by passing current. Reduction in coercive field with current density in Co/Pt can be consistently explained by Joule heating. On contrary, in Ni films we have identified a number of features inconsistent with the "thermal-only" scenario that can be considered as evidence of destabilization of magnetization by unpolarized electric current.

Linear single-error-correcting, double-error-detecting (SEC-DED) codes used for design of reliable memories cannot detect and can miscorrect some errors with large Hamming weights. In this paper we present several constructions of optimal nonlinear robust and partially robust codes, i.e. the Vasil’ev codes, the Phelps codes and the codes based on one switching constructions. The error detection and correction capabilities of these codes are analyzed and compared. We propose protection for memory devices based on extended Vasil’ev codes and extended Phelps codes. These nonlinear SEC-DEC codes have a minimum distance of four, fewer undetectable errors and fewer errors that are miscorrected than linear codes with the same dimension and redundancy. The extended Vasil’ev codes and the extended Phelps codes can provide for higher reliability in the presence of repeating errors or high rate of multi-bit-upsets. In this case replacing extended Hamming codes by the proposed codes may result in a drastic improvement in reliability of the memory with a reasonable cost in hardware overhead and power consumption. The architectures of memories based on these codes are described and the simulation results are presented illustrating their advantages over linear extended Hamming codes. Simple decoding algorithms for the nonlinear codes that can be used to provide concurrent error correction are presented. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.

We propose an efficient technique for the detection of errors in cryptographic circuits introduced by strong adversaries. Previously a number of linear and nonlinear error detection schemes were proposed. Linear codes provide protection only against primitive adversaries which no longer represents practice. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200–300%). Here we propose a novel error detection technique, based on the random selection of linear arithmetic codes. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (about 50% area overhead) due to the fact that no nonlinear operations are needed for the encoder and decoder.

Linear single-error-correcting, double-error-detecting (SEC-DED) codes used in the design of reliable memories cannot detect and can miscorrect errors with large Hamming weights. We propose protection for memory devices based on extended Vasil'ev codes. These nonlinear SECDED codes have a minimum distance of four, fewer undetectable errors and fewer errors that are miscorrected than linear codes with the same dimension and redundancy. The extended Vasil'ev codes can provide for higher reliability in the presence of repeating errors or high rate of multibitupsets. As far as we know, our paper is the only one discussing application of efficient nonlinear codes for design of reliable memories. The proposed approach can be applied to RAM, ROM, FLASH and disk memories with relatively low hardware overhead.

In this paper we consider the problem of constructing minimal cycle-breaking sets of turns for graphs that model communication networks, as a method to prevent deadlocks in the networks. We present a new cycle-breaking algorithm called Simple Cycle-Breaking or SCB algorithm that is considerably simpler than earlier algorithms. The SCB algorithm guarantees that the fraction of prohibited turns does not exceed 1/3. Experimental simulation results for the SCB algorithm are shown.

The adaptive and active nature of fault based side-channel attacks along with the large arsenal of fault injection methods complicates the design of effective countermeasures. To overcome the unpredictability of fault attackers protection methods based on robust codes were proposed which can provide uniform error detection against all errors eliminating possible weaknesses in the protection. In this paper we evaluate and compare the error detection properties and hardware overheads of architectures based on robust, partially robust, and minimum distance robust codes for both public and private key cryptosystems.