Dual (DMR) and Triple Modular Redundancy (TMR) are widely used techniques to provide fault detection and/or tolerance capabilities in safety-critical systems through - often diverse - redundancy. However, these systems remain vulnerable to adversarial attacks, which can mislead the AI models and lead to severe consequences. In this paper, we propose enhanced DMR and TMR implementations for image-based object detection leveraging image transformations during inference to mitigate the impact of adversarial attacks, hence addressing safety and security concerns simultaneously. Our approach achieves up to 12.9% and 12.2% higher accuracy in adversarial scenarios compared to stateof-the-art solutions in DMR and TMR configurations, respectively.
The relationship between cybersecurity and digital sovereignty is increasingly viewed as complementary. Cybersecurity focuses on the technical and operational protection of digital infrastructures, while digital sovereignty encompasses the political and strategic dimensions related to technological autonomy and the ability to regulate and make decisions. This intersection is particularly noticeable in technology and regulation-heavy sectors, such as the automotive industry, where vehicles are transforming into connected and intelligent platforms capable of generating, processing, and transmitting large amounts of data. In this context, protecting user privacy emerges as a critical challenge, closely linked to cybersecurity needs and the control over the cross-border flow of information. These dynamics show how difficult it is to coordinate cybersecurity, data management, and compliance across different countries, especially when foreign suppliers and supply chains are involved. Consequently, there is an urgent need for a coherent, shared, and relevant technical-conceptual framework that integrates operational requirements, fundamental rights, and strategic objectives. This paper proposes a semantic approach to analyze, systematize, and map emerging key concepts from normative sources, policy documents, and standards, using both expert-based approach and Artificial Intelligence models, to facilitate the extraction and organization of domain-specific terminology enhancing the population or enrichment of semantic resources. Results show the importance of controlled vocabularies, such as thesauri, which serve as fundamental tools for facilitating classification, interoperability, and for supporting normative production. In the case of the automotive sector, it becomes an operational support to address challenges related to cybersecurity, privacy protection, and regulatory autonomy.
Content Addressable Memory enables high-speed binary pattern matching and is widely used in various applications. Exploiting Resistive Random Access Memory (ReRAM) for CAM (ReCAM) realization offers advantages in terms of non-volatility, high density, and low power consumption using the Computation in Memory (CiM) concept. However, the unique defects of ReRAM combined with CMOS fabrication defects, introduce new faulty behaviors that complicate detection and diagnosis, thereby increasing the risk of test escapes and field failures. However, diagnosing faulty cells in ReCAM is crucial for analyzing failure mode, which helps improve manufacturing yield. It also promotes defect and fault tolerance both post-manufacturing and during runtime. Pinpointing faulty cells within the ReCAM array is particularly challenging, especially when all cells are connected to the same match-line (ML). Diagnosis also plays a critical role at runtime by enabling fault tolerance through mechanisms such as bypassing defective cells. This paper proposes a novel Design-for-Testability (DfT) approach for ReCAM diagnosis that utilizes infinitesimal voltage differences to identify the location of faulty cells. The proposed DfT circuitry and the accompanied diagnosis flow enhance diagnostic precision by enabling adjustable gain and sampling time in a multi-step process, effectively identifying faulty cells within the array. The simulation results of two distinct fault scenarios, applied to the binary patterns of all-match and all-mismatch conditions, demonstrate the effectiveness of the proposed DfT technique in achieving fine-grained fault detection across the ReCAM array. Furthermore, using this approach reduces the time complexity by more than half compared to the March-based approach with negligible overhead in area and power.
Convolutional Neural Networks (CNN), particularly those used in critical applications, such as autonomous driving, medical systems, and aerospace, require high reliability. While these algorithms exhibit inherent resilience, they remain sus-ceptible to Single-Event Effects (SEE) occurring at the hard-ware and impacting the model execution. These effects, usually induced by interactions with radiation particles, can lead to errors in electronic components, potentially causing incorrect inferences and increasing the risk of mispredictions. Meanwhile, quantization and pruning are widely employed to reduce the hardware footprint of CNN models, facilitating their deployment on embedded systems. Even when the models are reduced, CNN remain too large for an exhaustive fault injection campaign to assess their resilience. To address these challenges, we propose SFI4NN, a Statistical Fault Injection (SFI) framework specifically designed to evaluate the fault sensitivity of fixed-point quantized and pruned CNN architectures. Furthermore, we analyze the model resilience as a function of the pruning rate, showing that CNN sensitivity increases as pruning becomes more aggressive. The obtained results enable the development of hardware hardening strategies with reduced costs that are tailored to the reliability requirements of targeted applications. Experimental results demonstrate a 96 % improvement in resilience, with minimal hardware overhead compared to conventional hardening techniques such as triplication.
The quest for reliable testing of analogue and mixed-signal circuits remains a cornerstone in the advancement of integrated circuit technology, driving innovation in high-stakes areas such as aerospace and automotive systems. The continuous nature of the signals and the variability of the components make the task both time consuming and difficult to automate. This work presents a general methodology to detect parametric faults in analogue circuits using machine learning models combined with Monte Carlo simulations, advanced signal transformations and optimal classifier selection. The proposed framework is adaptable to different circuit architectures, as demonstrated by simulations of RLC bandpass filters and Sallen-Key filters. In particular, our approach incorporates new metrics that balance classification accuracy with implementation complexity and computational efficiency, providing a scalable solution adapted for automation and integration into an embedded test environment.
Physical Unclonable Functions (PUFs) provide a promising security mechanism by leveraging inherent process variations to generate unique, hardware-bound secrets without requiring secure storage. However, ensuring PUF reliability and detecting potential tampering remain critical challenges. This paper presents a fuzzy logic-based classification system that determines the authenticity of PUF responses using three key metrics: Reliability, Stability, and Reliability Invariance. The system classifies PUF responses into three categories: Trustable, Tampered, and Undecided. This approach enhances the automatic detection of unreliable responses that may indicate tampering while ensuring the fidelity of PUF responses over time. By applying fuzzy inference rules, our method achieves high accuracy in distinguishing between trustworthy and compromised PUFs. Experimental results demonstrate the effectiveness of our approach, making it a valuable method and tool for hardware security applications.
With the recent spread of Internet of Things (IoT) devices, security issues for hardware devices have been increasing. There are several methods proposed for analyzing power consumption of hardware devices to detect anomalous behavior of such devices. SARIMA is used to analyze steady-state time-series data, that is considered quite effective for detecting anomalous behavior of IoT devises. In this paper, we propose a method for detecting anomalous behavior of IoT devices based on a reference waveform using SARIMA. The proposed method extracts application power waveforms from measured power waveforms using the autoencoder. Then, a reference waveform is generated from the obtained application power waveforms using SARIMA, and compared to detect anomalous behaviors. We applied the proposed method to an IoT device implemented using the Raspberry Pi4, and succeeded in detecting anomalous behaviors by generating a highly accurate reference waveform using SARIMA, while the state-of-the-art recent method cannot detect them.
As semiconductor fabrication scales to smaller technology nodes, process variation has become a significant challenge, affecting power consumption, thermal behavior, and voltage stability in microprocessors and GPUs. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage, while maintaining a fixed frequency, has emerged as a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, AMD GPUs remain relatively unexplored, particularly in terms of process variation. This variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability under undervolted conditions, highlighting the impact of chip-to-chip variability. Our findings contribute to a deeper understanding of undervolting in AMD GPUs and its dependence on process variation, providing insights into practical power-saving strategies.
As memory cells continue to shrink in modern semiconductor technologies, radiation-induced Single Event Effects, such as single- and multi-bit upsets, pose growing challenges to system reliability. While effective and efficient for single and double-bit errors, traditional error detection and correction approaches, such as Error Correcting Codes (ECC), incur substantial overhead and complexity when designed to detect and correct multiple-bit errors. This study investigates the use of probabilistic data structures (PDS) as lightweight detectors for multiple-bit soft errors in memories. Leveraging the space-efficient and low-latency properties of Bloom filters, we implement a lightweight error detector (checker) within a representative memory subsystem on a flash-based FPGA. The checker's performance is validated through extensive neutron beam irradiation and fault-injection campaigns, demonstrating effective detection of multiple-bit errors with a tunable false-positive rate.
Designing a reliable and lightweight Physical Unclonable Function (PUF) is of prior importance in the context of hardware security. In this paper, a new variant of an arbiter PUF is proposed. Unlike the classical arbiter PUF that only compares the delay of two symmetrical paths, we propose to measure the path propagation delays and returns the time difference. Such measurements enable the arbiter PUF to be used in conjunction with techniques such as filtering of unreliable or low-entropy challenges and, thus, improve the global PUF performances. This ability is obtained thanks to an asynchronous Time-To-Digital Converter (TDC), which allows the measurements of the path delays. The proposed PUF benefits from the strengths of a classical arbiter PUF, such as the ability to extract a large number of challenge-response pairs at high throughput while improving reliability and entropy. This new arbiter PUF has been implemented on an FPGA and the results show it can achieve almost ideal values for metrics such as uniqueness, reliability and uniformity, simply by filtering the most unreliable responses.
Chiplet technology for 2.5-D/3-D integration is being rapidly adopted, including for System-on-Chips used in mission critical applications. We present a Total Ionizing Dose Effect study of a prototype Advanced Interface Bus (AIB) die-to-die interface in 28nm FD-SOI technology using pulsed x-rays and in-situ monitoring of the dose. Degradation of the maximum working frequency of the interface was observed due to the deposited dose. Using either the core voltage or the body bias voltage, we demonstrate that it is possible to partially recover this frequency loss. In space applications, this compensation, combined with in-situ dose monitoring, can be used to extend the life of 2.5-D/3-D circuits using high-speed die-to-die interfaces.
Microarchitectural side-channel attacks pose a significant threat to modern computing architectures. This paper presents a machine learning-based methodology for detecting these attacks using the gem5 simulator, focusing on the recently discovered Flush+Fault attack [6] on RISC-V. Our approach follows a three-phase process. The first phase is data collection, where we simulate attack and non-attack scenarios in gem5 and extract microarchitectural features indicative of side-channel activity. The second phase is the training phase, where we utilize machine learning (ML) techniques to build a classification model capable of distinguishing between normal execution and attack patterns. The last phase is the testing phase, where we evaluate the trained model using various performance metrics to validate its accuracy and precision. To the best of our knowledge, this is the first detection framework for Flush+Fault attacks [6] on RISC-V, showcasing its effectiveness in mitigating emerging threats. Our results indicate that gem5 metrics combined with machine learning models can reliably detect Flush+Fault attacks, achieving 0.99 accuracy with random forest (RF), 0.96 with support vector machine (SVM), and 0.95 with naive bayes (NB). Moreover, this methodology is adaptable to different side-channel attacks and architectures, making it a promising approach for strengthening microarchitectural security.
Split Computing has emerged as a promising paradigm for deploying Deep Neural Networks in Edge and Inter-net of Things systems, enabling inference tasks to be distributed between resource-constrained edge devices and cloud servers. This approach is particularly attractive for autonomous systems, where security and reliability may be critical. However, interme-diate feature maps transmitted between devices are vulnerable to corruption, which may result from intentional adversarial attacks or unintentional hardware faults. Distinguishing whether corruption originates from an external adversary or an inherent system fault is crucial for implementing appropriate counter-measures-reinforcing security mechanisms against attacks or improving system reliability to mitigate the effects of hardware-related faults. To the best of our knowledge, this work is the first to propose a machine learning-based classification mechanism capable of differentiating adversarial attacks from hardware defects in Split Computing systems. The proposed approach analyzes the intermediate feature maps transmitted from the edge device to the server, classifying the source of corruption to guide appropriate responses. Experimental results demonstrate that one of the proposed classifiers can distinguish between intentional and unintentional feature map corruptions with an accuracy of 93.91 %.
Attribute-Based Encryption (ABE) has been proposed to ensure the confidentiality of over-the-air (OTA) software updates in the automotive sector. Existing schemes predominantly rely on pairing-based cryptography, which is vulnerable to quantum computing attacks. This paper explores an ABE scheme based on Ring Learning with Errors (RLWE), a quantum-resistant cryptographic primitive. We implement a prototype on an embedded platform to assess the scheme's performance in terms of processing time and memory usage on the vehicle side. Results indicate that the RLWE-based ABE scheme can be efficiently integrated into OTA update frameworks with minimal performance overhead.
Compute-in-memory (CiM) based convolutional neural network (CNN) accelerators achieve low-power inference, utilizing memristive crossbar arrays for matrix multiplications. However, inherent conductance variations within the crossbar introduce computational errors. These errors propagate to the CNN output and cause image misclassification, leading to substantial accuracy degradation. This paper addresses the critical challenge of efficient and reliable post-manufacture testing for CiM-based CNN accelerators. We propose a novel test image sampling methodology, which iteratively applies sampled images from the CNN's testing dataset using progressive random sampling (PRS) to a device under test (DUT) and estimates a confidence interval for the DUT accuracy. Based on the confidence interval and the acceptable accuracy threshold, the test labels a DUT as "pass" or "fail". Furthermore, if we have access to an initial set of DUTs, we apply the images from the CNN's testing dataset to these DUTs and leverage the DUT outputs to rank-order test images. We develop a sequential estimation test (SET) framework, where the images from the CNN's testing dataset are sequentially applied according to a predetermined rank and the test terminates when a DUT can be confidently labeled as "pass" or "fail" based on the applied images. In each case, the number of applied test images adapts to the quality of the DUT. Experiments show that PRS and SET achieve 2.2x and 4.6x speedup compared to state-of-the-art test methodologies.
Spiking Neural Networks (SNNs) offer a promising computing paradigm suitable for low-power artificial intelligence. Spike-Timing Dependent Plasticity (STDP) is an unsupervised, biologically-inspired learning rule for SNNs. This work studies the reliability of STDP-trained SNNs under hardware faults which is largely unexplored. We present a thorough fault injection analysis of an STDP-trained SNN designed in Brian 2 simulator for MNIST classification. The analysis introduces faults in neurons and synapses before, during, and after training. We consider both permanent and transient, as well as single and multiple faults. We identify cases where the SNN exhibits inherent fault tolerance, cases where it adapts to faults through training, and cases where fault tolerance mechanisms are required,
This paper presents a way to improve the error correction capability of binary block error-correcting codes used in resistive memories. The proposed solution relies on a better exploitation of the bits suspected of being erroneously sensed. Once identified in a sensed memory word, such weak bits are flipped and error decoding is resumed with better chances of success. This works with an error-only decoder unable to handle any kind of soft information by itself. It is shown that the uncorrectable bit error rate can be reduced by up to an additional order of magnitude if the weak-bit information is leveraged not only in the presence of detectable uncorrectable errors but also in the case of certain conventionally undetectable errors. The same applies to the uncorrectable and undetectable bit error rate. These improvements can be achieved with limited latency and logic overhead, and without storage overhead.
Semiconductor supply chain vulnerability presents a significant obstacle to creating reliable systems. At various phases of the Integrated Circuit (IC) design life-cycle, malicious modifications, known as Hardware Trojans (HTs), can be introduced. Logic testing, a widely recognized approach for Automatic test pattern Generation (ATPG) in HT detection, encounters substantial challenges due to the vast complexity of the search space, making it impractical and leading to inadequate trigger coverage. This paper proposes a Particle Swarm Optimization (PSO) based method that leverages information on effective inputs to facilitate the detection of conditionally triggered ultra-small HTs. An evaluation of the technique on ISCAS-85 benchmarks reveals substantial improvements in trigger coverage and a notable reduction in runtime compared to state-of-the-art methods.
Predicting the Single-Event Effects in integrated circuits before their fabrication and ultimately estimating their cross-section would be of much interest to the space industry. For high-performance analog and mixed-signal circuits, radiation-hardening design flows routinely include Single-Event electrical simulation to identify the most sensitive nodes. If we can identify the sensitive area of the circuit to the PN-diodes connected to the sensitive nodes, we should thus be able to get an estimate of the cross-section. In this work, we show that this is far from being reality by comparing the results of electrical simulations to the cross-sections obtained by radiating a rad-hard reference generator for a high-performance ADC with Heavy Ions. A deep analysis of the results suggests that there are unmodelled effects at stake that dominate the experimental cross-section.
Program flow attacks involve disrupting the flow of instruction execution in microcontrollers (MCUs), thereby threatening their operation. While traditional studies focus on program counter or instruction corruptions within pipelines, little attention has been paid to the stages between FLASH memory and the CPU, such as memory accelerators. Body Bias Injection (BBI) is a fault injection technique in which a voltage pulse is applied to the backside of an integrated circuit, i.e. its substrate, causing localized disruptions in the power network. Despite its proven effectiveness in inducing transient faults, to the best of our knowledge, there is no information on its impact on MCU program flow. Within this context, this paper demonstrates that BBI can efficiently disrupt MCU program flow, causing entire instruction lines to be skipped or repeated. It also shows that the most sensitive part of the MCUs against BBI is likely to be the memory accelerator rather than the processor itself.
