Due to the distributed nature of PCB design, manufacturing, and distribution process, recycled, cloned, and overproduced PCBs can easily infiltrate the supply chain. To mitigate these threats, PCB authentication techniques can be used to help distinguish original PCBs from the counterfeit ones. Malicious alteration of PCBs in the field is also a serious security concern as it enables an attacker to bypass restrictions imposed by the original equipment manufacturers. An intelligent form of tampering could lead to an unauthorized use of the system, leakage of secret information, and extraction of an IP (such as designs and algorithms). In this chapter, we discuss various methods to authenticate PCBs and validate their integrity against tampering efforts.

Scan-based test is commonly used to increase testability and fault coverage. IEEE Standard 1149.1 defines test logic included in a design to test the interconnections between chips, and observe and control on-chip logic. However, these features have been exploited by the attackers to steal critical information, pirate intellectual property (IP) design, or illegally take control of the chip. Over the past decade, researchers in industry and academia have extensively studied, and developed, defenses to address the potential threats. This chapter first introduces the relationship between testability and security, then discusses the scan-based and JTAG attacks, and defenses for these threats, respectively.

PCBs of electronic systems are deemed robust, secure, and trustworthy. However, numerous instances of PCB design exploitation in design houses, foundries, and fields of operation have given rise to major security concerns. Examples of physical tampering of PCBs include malicious alterations, such as adding or replacing a component through soldering, bypassing a connection, or snooping a trace to change or disrupt system functionality. An adversary can obtain critical data from a PCB or bypass a security mechanism through these malicious modifications. Thus, it is possible for an attacker to gain illegal access to secure systems and leak information, or disrupt the functionality of target designs. Unfortunately, the growing complexity and manufacturing cost of modern PCBs has led to a highly distributed supply chain and increased reliance on third-party entities. Consequently, it is extremely difficult to ensure impenetrable security at every phase of PCB lifecycle and ensure safety against the physical attacks on PCBs. In this chapter, we discuss possible attack models on PCBs and demonstrate instances of hardware Trojan insertion in fabricated PCBs that can either cause malfunction, or leak secret information. We review the effectiveness of traditional PCB test methodologies in detecting hardware Trojans in PCB. We also demonstrate an attack scenario of in-field alteration of PCBs via Modchip attacks.

This chapter describes system-level attacks, with specific focus on software attacks that exploit functional or side-channel bugs in hardware. It presents SoC design flow, including definition of security architecture and design review to ensure security. It also describes security policy-based solutions that govern confidentiality, integrity, and availability of security assets in an SoC to provide effective countermeasures against these attacks.

With the advent of system on chip (SoC), the issues related to design, verification, debug, and testing of SoCs have become more complex and challenging compared with those of a single block or an intellectual property (IP) core. This chapter first introduces the background on very large scale integration (VLSI) testing and the IP-based SoC lifecycle, then briefly discusses the issues associated with design, verification, debug, and test at the SoC level. Thereafter, methodologies for design-for-debug and design-for-testability are presented in this chapter.

Side-channel attacks (SCAs) aim at extracting secrets from a chip or a system, through measurement and analysis of physical parameters. Examples of such parameters include supply current, execution time, and electromagnetic emission. These attacks pose a serious threat to modules that integrate cryptographic systems, as many side-channel analysis techniques have proven successful in breaking an algorithmically robust cryptographic operation (for example, encryption) and extracting the secret key. In this chapter, we focus on different side-channel attack modalities in hardware implementations of cryptographic algorithms. Chapter 16, on the other hand, covers side-channels in a processor micro-architecture, which can be controlled by a software, and are visible through it. We discuss the analysis techniques that can be applied on various side-channel parameters to retrieve cryptographic keys. Next, we describe possible countermeasures, based on design modifications, to mitigate side-channel attacks. Finally, we point to various metrics that can be used to quantify the amount of information leakage in a side-channel parameter, and discuss ways to provide resistance to SCAs.

Physical attacks are capable of compromising confidentiality and integrity provided by modern cryptography through observing a chip's silicon implementation. Such attacks are especially threatening to chips with intellectual property (IP) values, and the ICs deployed in smartcards, smartphones, military systems, and financial systems relying on processing sensitive information. Reverse engineering, microprobing attack, and invasive fault injection attack are the most common physical attacks. This chapter introduces these physical attacks and their countermeasures, respectively.

Hardware security primitives play an important role in ensuring trust, integrity, and authenticity of integrated circuits (ICs) and electronic systems. Primitives, such as physical unclonable functions (PUFs) and true random number generators (TRNGs) produce device-intrinsic electronic fingerprints and random digital signatures, respectively, to generate cryptographic keys and IDs commonly used for device authentication, cloning prevention, generating session keys, nonce, and many more. Further, designs, such as combating die and IC recycling (CDIR) sensors offer countermeasures against IC counterfeiting (recycling), which is of a significant concern in the modern electronic supply chain. In this chapter, common hardware security primitives and designs for countermeasures against various threats, and vulnerabilities are discussed. First, the device-intrinsic properties are briefly discussed as these features play key roles in designing various security primitives. Following, hardware security primitives—namely PUF and TRNG—and designs for anticounterfeit (DfAC) are explained in detail with multiple examples and relevant applications. The chapter ends with a brief look at post-CMOS security primitives designs equipped with emerging nanoscale electronic devices.

This chapter provides an overview of the various forms of hardware IP security issues that are common in the ASIC life cycle. We also discuss various IP security issues that are present in the FPGA-based system development process.

This chapter describes hardware obfuscation as a design solution to protect hardware IP against various attacks in its lifecycle, including reverse engineering and piracy. Various approaches for obfuscation, their relative effectiveness, and weaknesses are discussed.

This chapter gives an introduction about the emerging threats and issues of hardware security and trust. An overview of the levels of abstraction for computing systems is provided as well as the attacks, vulnerabilities, and countermeasures observed in every level. The chapter gives a brief historical perspective on the evolution of hardware security, and introduces a hands-on approach to implement a number of attacks and protection mechanisms on a custom hardware platform.

With the advent of globalization, similar to many other industries, the electronics and semiconductor industries have adopted a horizontal business model, where many entities located around the globe are involved in the hardware design flow. Although this model has lowered time-to-market and manufacturing costs through outsourcing and design reuse, it has also introduced security and trust issues in the final product. In this chapter will discuss the composition of modern electronic hardware supply chain, the security and trust issues associated with it, and the potential countermeasures to these concerns.

This chapter presents pre-silicon and post-silicon security and trust assessment techniques. Pre-silicon assessment techniques analyze vulnerabilities of a hardware design and assess its security at various stages of design process, including register-transfer level (RTL), gate-level netlist, design-for-test (DFT) insertion, and physical design. On the other hand, post-silicon assessment techniques aims to identify security and trust issues in the fabricated integrated circuit (IC). The design for security and trust techniques, which provide additional resources in the hardware to make it inherently resilient to different attacks, for example, Trojan insertion, fault injection, and side-channel attacks, are discussed next.

This chapter provides a quick overview of electronic hardware, such as nanoscale transistor technologies, digital logic, circuit theory, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), printed circuit boards (PCBs), embedded systems, and the interaction between hardware, firmware, and software.

A Printed Circuit Board (PCB) is one of the basic building blocks of any electronic system. The primary criteria for any functional and operational electronic system are valid interconnection and assembly of all the components in a design. PCBs act as the cornerstone of any hardware system by facilitating electrical connection and mechanical support of the active and passive components. A good knowledge of PCB is essential to better understand electronic hardware and security issues which lie therein. In this chapter, a comprehensive overview of modern PCBs is provided with a special focus on design and testing approaches. The chapter outlines the key aspects of building a fully operational PCB-based system with an elaborate description of every stage of the life cycle.

Countermeasures designed to protect system-on-chip (SoC) from intellectual property (IP) counterfeiting are inadequate for heterogeneously integrated systems-in-packages (SiP) due to shifts in manufacturing flow. Additionally, traditional obfuscation methods are now compromised by emerging deobfuscation techniques. This paper introduces network-on-chip (NoC) obfuscation, NoXLock, to effectively safeguard the IP of SiP designs. By obfuscating the routing algorithm, the performance of unauthorized SiPs, including throughput and packet loss, is effectively constrained. To securely activate the system, a novel method utilizing dynamic traffic patterns is proposed. Extensive security analyses and experimental results in this paper demonstrate that NoXLock resists state-of-the-art attacks, including oracle-guided SAT, oracle-less removal, and probing-based methods, without imposing a significant penalty on power, performance, and area (PPA) overheads.

System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.

Battery-powered technologies like pagers and walkie-talkies have long been integral to civilian and military operations. However, the potential for such everyday devices to be weaponized has largely been underestimated in the realm of cybersecurity. In September 2024, Lebanon experienced a series of unprecedented, coordinated explosions triggered through compromised pagers and walkie-talkies, creating a new category of attack in the domain of cyber-physical warfare. This attack not only disrupted critical communication networks but also resulted in injuries, loss of life, and exposed significant national security vulnerabilities, prompting governments and organizations worldwide to reevaluate their cybersecurity frameworks. This article provides an in-depth investigation into the infamous Pager and Walkie-Talkie attacks, analyzing both technical and non-technical dimensions. Furthermore, the study extends its scope to explore vulnerabilities in other battery-powered infrastructures, such as battery management systems, highlighting their potential exploitation. Existing prevention and detection techniques are reviewed, with an emphasis on their limitations and the challenges they face in addressing emerging threats. Finally, the article discusses emerging methodologies, particularly focusing on the role of physical inspection, as a critical component of future security measures. This research aims to provide actionable insights to bolster the resilience of cyber-physical systems in an increasingly interconnected world.

The rapid demand for efficient AI hardware has driven the adoption of advanced packaging technologies such as 2.5D/3D integration. By enabling tight integration of CPUs, accelerators, and high-bandwidth memory (HBM) on a single silicon interposer, these technologies significantly boost performance, power efficiency, and memory bandwidth. However, this chiplet-based approach introduces new security challenges-most notably, increased risks of intellectual property (IP) piracy, reverse engineering (RE), and counterfeiting. This paper introduces a hierarchical co-obfuscation strategy that secures every layer of SiP-based AI hardware-from the package level down to the die level-fortifying both the interconnect network and compute chiplets. Our approach leverages hardware metering, locking mechanisms, split manufacturing, and sequential obfuscation to protect against both hardware- and software-based attacks, all while imposing minimal performance overhead ((1) over tilde1%). The scheme further supports a keyless activation mechanism for hardware licensing, making it highly scalable for large high-performance computing (HPC) deployments.