Globalization of the System-on-Chip (SoC) supply chain has resulted in increased intellectual property (IP) piracy, illegal reuse, and tampering by malicious actors. In response to these challenges, IP watermarking presents itself as a promising solution to protect against these risks; however, traditional methods rely heavily on labor-intensive manual tests by verification engineers and fail to account for the potential threat posed by malicious SoC design houses. To overcome these challenges and improve the efficiency of the watermark verification process while safeguarding against possible attacks, we developed ActiWate as an innovative watermarking approach that not only provides proof of authorship but also prevents unauthorized usage of an IP. Using an automatic self-verification technique, the watermark establishes communication with various peripherals within the SoC. The versatility and effectiveness of ActiWate have been proven through extensive experiments on multiple SoCs with diverse components and peripherals, including the testing of watermarking and the verification of various IPs. Moreover, we discuss the inclusion of this multiple serialized verification in more case studies and results, as well as analyzing prominent security threats, including reverse engineering attacks.

Countermeasures designed to protect system-on-chip (SoC) from intellectual property (IP) counterfeiting are inadequate for heterogeneously integrated systems-in-packages (SiP) due to shifts in manufacturing flow. Additionally, traditional obfuscation methods are now compromised by emerging deobfuscation techniques. This paper introduces network-on-chip (NoC) obfuscation, NoXLock, to effectively safeguard the IP of SiP designs. By obfuscating the routing algorithm, the performance of unauthorized SiPs, including throughput and packet loss, is effectively constrained. To securely activate the system, a novel method utilizing dynamic traffic patterns is proposed. Extensive security analyses and experimental results in this paper demonstrate that NoXLock resists state-of-the-art attacks, including oracle-guided SAT, oracle-less removal, and probing-based methods, without imposing a significant penalty on power, performance, and area (PPA) overheads.

Due to the perils posed by side-channel attacks and the critical limitations of existing post-silicon assessment solutions, such as low flexibility and extensive expertise requirements, the demand for pre-silicon side-channel security verification has increased significantly. In this paper, we present a novel approach for electromagnetic (EM) side-channel leakage assessment at the gate-level abstraction. More specifically, our framework builds a design-agnostic EM leakage model by focusing on switching activities of registers, the main contributor to in-field EM side-channel emissions, and register fanouts to provide a high-confidence indication of design leakiness. Additionally, empirical layout-level data is back-annotated to the EM model for simulating gate-level estimated EM traces and calculate security metrics to quantify design-level leakage. Our approach ensures the utmost flexibility in deploying countermeasures since it evaluates side-channel leakage behavior accurately at an early design stage. More importantly, designs with information leakage can be detected in early stage, significantly reducing the secure design time and the need for iterative layout-level simulations. To demonstrate the effectiveness of our approach, we conduct extensive experiments on AES benchmarks, showing that the designs identified as leaky at the gate-level consistently exhibit leakiness in post-silicon assessments (FPGA prototyping). This highlights the potential of our approach for early stage security evaluation and the reduction of design iterations required for achieving robust EM side-channel resistance.

Leveraging the intellectual property (IP) core is a widely adopted strategy to expedite the development of new products within modern system-on-chip (SoC) architectures. In today's competitive market, reusing and sharing IP cores can significantly shorten the time-to-market for SoC designs. However, this practice also introduces security problems, such as IP piracy and overuse. Watermarking is one of the most popular methods to combat IP counterfeiting. Nevertheless, the current state-of-the-art watermarking approaches often overlook the threat posed by rogue SoC design houses and frequently require physical access to the target IP in the SoC for watermark (WM) authentication. To address these issues, this article proposes GEM-Water, an effective IP/SoC-agnostic WM verification mechanism that utilizes the electromagnetic (EM) radiation emitted by an IP within a packaged SoC to verify the WM during SoC boot-up. Based on secret authorship information, the functional finite state machine (FSM) of the target IP is modified and subsequently translated into an EM signature. This signature can later be extracted using a near-field EM probe during SoC boot-up. With the assistance of such EM side-channel analysis, GEM-Water can authenticate the WM without the need for physical access to the target IP itself. To validate the robustness and viability of GEM-Water, experiments were conducted on various AMD Xilinx 7 series and Microsemi FPGAs, demonstrating WM detection accuracy consistently exceeding 95% across different benchmarks.

System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.

As large language models (LLMs) continue to be integrated into modern technology, there has been an increased push towards code generation applications, which also naturally extends to hardware design automation. LLM-based solutions for register transfer level (RTL) code generation for intellectual property (IP) designs have grown, especially with fine-tuned LLMs, prompt engineering, and agentic approaches becoming popular in literature. However, a gap has been exposed in these techniques, as they fail to integrate novel IPs into the model's knowledge base, subsequently resulting in poorly generated code. Additionally, as general-purpose LLMs continue to improve, fine-tuned methods on older models will not be able to compete to produce more accurate and efficient designs. Although some retrieval augmented generation (RAG) techniques exist to mitigate challenges presented in fine-tuning approaches, works tend to leverage low-quality codebases, incorporate computationally expensive fine-tuning in the frameworks, or do not use RAG directly in the RTL generation step. In this work, we introduce DeepV: a model-agnostic RAG framework to generate RTL designs by enhancing context through a large, high-quality dataset without any RTL-specific training. Our framework benefits the latest commercial LLM, OpenAI's GPT-5, with a near 17% increase in performance on the VerilogEval benchmark. We host DeepV for use by the community in a Hugging Face (HF) Space: https://huggingface.co/spaces/FICS-LLM/DeepV.

The rapid demand for efficient AI hardware has driven the adoption of advanced packaging technologies such as 2.5D/3D integration. By enabling tight integration of CPUs, accelerators, and high-bandwidth memory (HBM) on a single silicon interposer, these technologies significantly boost performance, power efficiency, and memory bandwidth. However, this chiplet-based approach introduces new security challenges-most notably, increased risks of intellectual property (IP) piracy, reverse engineering (RE), and counterfeiting. This paper introduces a hierarchical co-obfuscation strategy that secures every layer of SiP-based AI hardware-from the package level down to the die level-fortifying both the interconnect network and compute chiplets. Our approach leverages hardware metering, locking mechanisms, split manufacturing, and sequential obfuscation to protect against both hardware- and software-based attacks, all while imposing minimal performance overhead ((1) over tilde1%). The scheme further supports a keyless activation mechanism for hardware licensing, making it highly scalable for large high-performance computing (HPC) deployments.

As the semiconductor industry shifts to heterogeneous system-in-package (SiP) technologies to overcome the limitations of Moore's Law and Dennard scaling, the integration of modular intellectual property (IP) blocks (e.g., chiplets) significantly changes the threat vectors and introduces new system-level threats with increased vulnerability, such as remote fault injection (RFI) attacks, runtime malicious activity, and runtime probingbased attacks. Traditional security measures for monolithic system-on-chips (SoC) are inadequate due to their inability to either handle multiple runtime threats simultaneously or address the change of threat models due to the unique characteristics of heterogeneous systems. To address these challenges, we develop a reconfigurable root-of-trust (RoT) hardware security module to detect and respond to any RFI attack, runtime malicious activities, or probing-based attacks, thereby safeguarding the system's confidentiality and integrity without needing multiple and separate security solutions. Its reconfigurability allows a system designer to easily incorporate other runtime security features and upgrade the existing security features, providing reassurance about its long-term effectiveness. We utilize an FPGA board to implement and validate the effectiveness of the hardware security module in detecting several runtime threats with minimal overheads.

The increasing complexity and performance demand of modern electronic systems have led to widespread adoption of Heterogeneous Integration (HI) through advanced System-in-Package (SiP) technologies. These architectures integrate diverse chiplets onto a common interposer to enable modular design, improved performance, and reduced cost. However, such integration introduces new runtime security vulnerabilities, particularly across the inter-chiplet communication facilitated by Network-on-Chip (NoC) interconnects. Traditional system-on-chip (SoC) security solutions are inadequate in this context due to the heterogeneity of chiplets and the lack of unified control across vendors and already fabricated blackbox chiplets. In this work, we propose RunSiP, a property-based runtime security monitoring framework for NoC-based SiP architectures. RunSiP integrates Distributed Runtime Security Monitors (DRSMs) into the Chiplet Hardware Security Module (CHSM) to dynamically enforce security policies during runtime. These policies are generated based on SiP and chiplet specifications, identifying potential attack vectors and guiding policy enforcement across the distributed NoC. RunSiP monitors and detects violations of confidentiality, integrity, and secure communication during inter-chiplet data exchange. We demonstrate the RunSiP framework on a Xilinx Kintex UltraScale 2.5D FPGA platform and show its effectiveness in detecting various runtime security violations with minimal performance overhead. Our framework provides a scalable and modular solution for safeguarding SiP designs, ensuring secure runtime operation even in the presence of untrusted or compromised chiplets.

With the desire for hardware design automation, large language models (LLMs) are being increasingly incorporated into the IC design flow to assist in register transfer level (RTL) generation, IP development acceleration, reduction of time-to-market (TTM), and satisfying the demands of modern applications such as AI accelerators. However, they do not incorporate security considerations when generating the designs. Our initial investigation reveals that RTL code created by leading LLMs such as OpenAI’s ChatGPT [1], Google DeepMind’s Gemini [2], and xAI’s Grok [3] can exhibit important security flaws, such as improper handling of registers, nonsecure datapaths, and missing access controls, that may lead to information leakage or system malfunction in security-critical applications. Of 42 LLM-generated designs on 7 different models, 74% of the designs contained at least one security vulnerability that compromises the confidentiality, integrity, and availability of these designs. Although AI-driven automation presents a significant benefits in hardware design flows, our study indicates that RTL designs are not secure and specific mechanisms should be taken to mitigate vulnerabilities while using the benefits of LLMs. From this paper’s security investigation, we can sufficiently suggest that using CWE-guided prompting, formal property checks, and FSM-level structural validation can help mitigate vulnerabilities during LLM-guided RTL generation.

In order to maintain the historical progress of CMOS technology and comply with Moore's Law, heterogeneous integration (HI) integrates separately manufactured chiplets onto an interposer substrate to create systems that resemble system-on-chip (SoC) structures, which are now more widely known as system-in-package (SiP). Heterogeneously integrated SiP designs based on chiplets continue to improve in transistor density despite the slowing rate of Moore's Law, satisfying strict time-tomarket requirements while minimizing area and cost. However, concerns about SiP intellectual property (IP) overproduction, reverse engineering, and IP infringement arise as advanced packaging methods emerge. The attackers would like to gain a competitive edge by illicitly acquiring confidential IP, leading to potential repercussions such as IP loss and overproduction. While hardware-focused solutions like traditional hardware metering offer IP protection, safeguarding chiplets and entire systems in 2.5D/3D SiPs demands advancements beyond traditional approaches used in 2D monolithic SoC designs. This paper introduces SiPMeter, an innovative hardware metering technique for SiP architectures leveraging open-market chiplets. SiPMeter utilizes inter-chiplet interactions through interposers to prevent chiplet(s) re-use and tracing SiPs in the heterogeneous integration supply chain. Interactions are also protected using Shamir-Secret-Sharing, allowing SiP integrators to confidentially enable hardware metering throughout the system from cloning, misuse, and attacks.

As the semiconductor industry adopts system-in-package (SiP) technologies to address the limitations of Moore's Law and Dennard scaling, the increasing complexity of heterogeneous integration (HI) makes efficient physical fault injection attacks much more challenging to execute. Hence, skilled attackers attempt to compromise the device's confidentiality, integrity, or availability through remote fault-injection (RFI) attacks without physical access to the target system. In this case, this transformative shift of the threat models and evolving threats associated with RFI attacks render the traditional countermeasures incompatible. To overcome these challenges, we propose ReFID, a system-wide RFI attack detection and mitigation strategy for heterogeneous systems, by placing on-chip sensors and developing a system-level root-of-trust (RoT) module. The RoT module implemented as an embedded FPGA (e-FPGA) controls the sensors and analyzes the run-time sensor data to detect malicious activities within a trusted region of a heterogeneous system caused by remote attacks. Upon detecting any fault, it immediately creates uncontrollable scenarios to prevent an attacker from exploiting the impact of an RFI attack. We execute a combination of remote overclocking and undervolting attacks on a crypto application within the trusted execution environment of a CPU-FPGA heterogeneous system to showcase the ReFID's efficacy.

Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, comprehensiveness, and adaptability. The advent of large language models (LLMs), with their remarkable capabilities in natural language understanding, code generation, and advanced reasoning, presents a new paradigm for tackling these issues. Moving beyond monolithic models, an agentic approach allows for the creation of multi-agent systems where specialized LLMs collaborate to solve complex problems more effectively. Recognizing this opportunity, we introduce SV-LLM, a novel multi-agent assistant system designed to automate and enhance SoC security verification. By integrating specialized agents for tasks like verification question answering, security asset identification, threat modeling, test plan and property generation, vulnerability detection, and simulation-based bug validation, SV-LLM streamlines the workflow. To optimize their performance in these diverse tasks, agents leverage different learning paradigms, such as in-context learning, fine-tuning, and retrieval-augmented generation (RAG). The system aims to reduce manual intervention, improve accuracy, and accelerate security analysis, supporting proactive identification and mitigation of risks early in the design cycle. We demonstrate its potential to transform hardware security practices through illustrative case studies and experiments that showcase its applicability and efficacy.

Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated circuit design and the continuous upgrading of security requirements, the SVA development model has exposed major limitations. It is not only inefficient in development, but also unable to effectively deal with the increasing number of security vulnerabilities in modern complex integrated circuits. In response to these challenges, this paper proposes an innovative SVA automatic generation framework SVAgent. SVAgent introduces a requirement decomposition mechanism to transform the original complex requirements into a structured, gradually solvable fine-grained problem-solving chain. Experiments have shown that SVAgent can effectively suppress the influence of hallucinations and random answers, and the key evaluation indicators such as the accuracy and consistency of the SVA are significantly better than existing frameworks. More importantly, we successfully integrated SVAgent into the most mainstream integrated circuit vulnerability assessment framework and verified its practicality and reliability in a real engineering design environment.

Power side-channel (PSC) vulnerabilities present formidable challenges to the security of ubiquitous microelectronic devices in mission-critical infrastructure. Existing sidechannel assessment techniques mostly focus on post-silicon stages by analyzing power profiles of fabricated devices, suffering from low flexibility and prohibitively high cost while deploying security countermeasures. While pre-silicon PSC assessments offer flexibility and low cost, the true nature of the power signatures cannot be fully captured through RTL or gate-level design. Although physical design-level analysis provides precise power traces, collecting data is time and resource-consuming at the layout level. To address this challenge, we propose, for the first time, a fast and efficient physical design-level PSC assessment framework using a graph neural network (GNN). This framework predicts dynamic power traces for new layouts, using them to assess physical design security through metrics evaluation. Our experiments on AES-GF layout implementations achieve a tremendous 133x speedup compared to conventional simulation-based flow without sacrificing substantial accuracy.

As the complexity of System-on-Chips (SoCs) increases, ensuring their security presents escalating challenges. Formal property verification is one of the most robust methods to model and check security behaviors using model checkers. However, the generation of these security properties is a labor-intensive endeavor. Large language models (LLMs) have been applied in multiple fields due to their excellent ability to understand natural language. Hence, this paper presents a novel framework that utilizes LLMs to automate the generation of security properties directly from Register Transfer Level (RTL) designs. By extracting critical features and security assets from both the design specifications and RTL, the framework systematically produces tailored security properties for specific hardware designs. These properties are systematically cataloged in a security property database, providing an essential resource for ongoing and future hardware verification efforts. The effectiveness of this innovative framework is validated through its application to various open-source hardware designs, confirming its ability to significantly improve SoC security verification by efficiently generating robust security properties.

Abstract A system-in-package (SiP) design takes advantage of cutting-edge packaging technology and heterogeneous integration (HI) in response to the growing need for aggressive time-to-market, high-performance, less expensive, and smaller systems. However, aggregating dies with different functionalities introduces new attack vectors with fault-injection attacks (FIA) that can effectively alter a circuit's data and control flow maliciously to cause disruptions of secure communication or sensitive information leakage. Additionally, traditional threat models associated with FIA on a 2D monolithic system-on-chip (SoC), and the corresponding mitigation techniques may not be compatible with modern 2.5D and 3D SiP architectures. To address these limitations, we propose system-aware fault injection attack detection for SiP architectures (SYSFID), a real-time and on-chip sensor-based fault monitoring approach integrated into a system-level design. SYSFID detects any fault-induced anomalous alterations in path delays of the components of inter-chiplet networks by strategically placing on-chip fault-to-time converter (FTC) sensors and controlling them efficiently to safeguard overall system security. To demonstrate the effectiveness of SYSFID, we detect several fault injection attempts on the FPGA implementation of a network-on-chip (NoC) based architecture during secure network packet transfers. Our experiments also illustrate that the SYSFID framework reliably senses both global and local FIAs with minimal overheads.

Systems on Chips (SoCs) are integral to modern devices, from consumer electronics to critical applications in healthcare, finance, and defense, housing various vital assets. Ensuring comprehensive security verification is crucial to protect these assets from diverse vulnerabilities. However, traditional security verification is time-consuming, and the rapid pace of market-driven design cycles demands new versions within tight time-to-market windows. Conducting exhaustive security verification from scratch for each new design iteration is both challenging and impractical. This paper introduces a novel framework leveraging large language models (LLMs) to translate security properties from legacy designs to new versions at the Register Transfer Level (RTL). By reusing existing verification efforts, this approach significantly reduces verification time while maintaining security continuity. Our methodology not only trans-lates but also extends and expands security properties to detect new vulnerabilities. Experimental results demonstrate substantial improvements in security continuity and vulnerability detection, advancing hardware security verification for evolving SoCs.

As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic devices, incorporating security into an SoC design flow poses significant challenges. Existing security solutions are inadequate to effectively verify modern SoC designs due to their limitations in scalability, comprehensiveness, and adaptability. On the other hand, large language models (LLMs) are celebrated for their remarkable success in language understanding, advanced reasoning, and program synthesis tasks. Recognizing an opportunity, our research explores leveraging the emergent capabilities of generative pre-trained transformers (GPTs) to address the existing gaps in SoC security, aiming for a more efficient, scalable, and adaptable methodology. By integrating LLMs into the SoC security verification paradigm, we open a new frontier of possibilities and challenges to ensure the security of increasingly complex SoCs. This paper offers an in-depth analysis of existing works, presents practical case studies, and demonstrates comprehensive experiments. We also present the achievements, prospects, and challenges of employing LLM in different SoC security verification tasks.