As semiconductor device scaling continues, the critical dimension CD has continued to decrease. The required CD for advanced device nodes is now beyond the resolution limit of deep ultraviolet (DUV) lithography and extreme ultraviolet lithography (EUVL) is now widely used to meet resolution requirements. Despite continuous improvements in the performance of photoresists, masks, and post-lithography processes, stochastic defects, or stochastic failures (5) - space bridges and line breaks - are still a major factor of yield loss in production(14). Detecting, characterizing, and repairing stochastic defectivity using experimental methods alone is expensive, requiring a lot of wafers, metrology resources and time (9, 15). We discuss a cost-effective predictive failure probability model - a virtual inspector - and demonstrate how it is an essential tool for the study and reduction of stochastic defectivity in EUVL. We use rigorous probabilistic lithography modeling to construct accurate failure probability models FPMs for EUVL. The computing rate of the FPM admits virtual inspection of full layouts. We confirm that the defectivity predictions of the FPM align well with large-area e-beam inspection results. We demonstrate that the FPM can be used to find the optimal patterning condition and the optical proximity correction OPC that minimize stochastic failures in an EUVL process.

In recent years, the overlay budget requirements have tightened significantly across various lithographic technologies. Both DUV multiple patterning and EUV lithography introduce unique alignment errors due to pattern shift. Traditionally, most overlay improvements have been achieved by hardware advancements. However, predicting on-device overlay using aberration fingerprints can provide valuable insights, as the projection optics module plays a key factor in determining the distortion of the overlay, in terms of pattern placement error control in lithography systems. In this paper, we demonstrate how computationally calculated overlay of the device pattern, using lens aberration fingerprints as an additional input, can be utilized to predict pattern shift and effects such as non-zero offset/overlay. This offset is a critical parameter in the field of semiconductor lithography, representing the residual misalignment between different layers of a semiconductor device after various processing steps. Non-zero offset acknowledges and quantifies the inevitable deviations that occur during manufacturing: such deviations can arise from multiple sources, including tool inaccuracies, process variations, and metrology. It is measured as the difference between on-target overlay after lithography vs. on-device measurement after etching. For enhanced process control required for the latest nodes, the objective is to characterize the non-zero offset, minimize its magnitude and variability, and identify potential excursions across tool fleet, layers, slit position and exposure conditions. This work focuses on characterizing non-zero offset through data collection and computational lithography. With the availability of wafer-fine aberration data, automating this process is feasible and detailed in this paper. Integrating such measurement into the overlay control loop allows for quantifying its benefits.

The critical dimensions of advanced semiconductor manufacturing processes have decreased to a few tens of nanometers while the aspect ratios have increased beyond 100. The performance of plasma etch patterning processes as well as the cost and time of the development cycle are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a computational patterning software, ProETCH®, has been developed with rigorous physics and advanced algorithms for modeling the etch patterning process, with the featured capabilities in calibrating the reaction mechanisms and optimizing the etch process. A shallow trench isolation etch process using self-aligned double patterning was investigated. A reaction mechanism of silicon etch by Ar/Cl2 plasma was developed to address the surface reactions, and a plasma hypermodel was introduced to correlate process operating conditions to plasma parameters at the wafer surface. The parameters of the reaction mechanism and the plasma hypermodel were calibrated with experimental data obtained from cross-sectional scanning electron microscope (XSEM) images. The calibrated model is used to identify the different fundamental pathways that contribute to the observed profile metrics in XSEMs. The model was then used for process development and optimization by solving the forward and inverse problems. In the forward problem, the model is used to predict the etching profile at different process conditions. Predictions for both interpolation conditions (process parameters within the range used for developing the model) and extrapolation conditions (process parameters outside of the range used for developing the model) agree well with the experimental data with the root mean square error less than 4 nm (1 nm resolution used for the mesh). In the inverse problem, the developed model is used to search for process conditions (e.g., values of bias power and pressure), which could result in desirable profiles. The solutions to the inverse problem demonstrate a degeneracy in process space of the etching process for a given target profile.

Understanding the origins and propagation of defects and hotspots in patterning processes used for semiconductor fabrication is of paramount importance in managing yield. In this paper, results from physics-based simulators to model lithography and dry etch processes are presented and compared to experimental results. These models are used to study different types of hotspots and defects observed in a litho-etch-litho-etch (LELE) multipatterning process. At each pass of the LELE flow, patterns are printed into a SiO2 collecting layer using a trilayer film stack comprised of a negative tone photoresist layer, a spin-on-glass layer (SOG), and a spin-on-carbon layer (SOC). After both passes of the LELE process, the patterns in the SiO2 collecting layer will be transferred to a TiN hardmask prior to final etch into an underlying dielectric. The SOG and SiO2 layers are etched using fluorocarbon plasma, while the SOC layer is etched with an H2/N2 plasma generated in a capacitively coupled plasma source. A pinching hotspot is observed during the single litho-etch pass in a region where two features are placed very close and the image contrast is low. However, for some lithography process conditions, this hotspot is rectified by subsequent etch steps and does not always transfer as a defect into the SiO2 layer. The quenching of the hotspot occurs primarily during the etching of the SOC layer due to the aspect ratio-dependent etching (ARDE) effect. A bridging hotspot is also observed at lithography during the single litho-etch pass at high exposure doses. This hotspot, on the other hand, is exacerbated by the etch steps because of the ARDE effect. Hotspots are also identified that originate from overlay errors between photomasks exposed during first and second passes of the LELE process. The etch bias generated during etching of the SOG layer is crucial to ensure that the overlay-related hotspot does not translate to the SiO2 layer. The extent of etch bias in the SOG etch step is critical and can be tuned by adjusting the neutral to ion flux ratio during that etch step. Increasing the flux ratio improves the process window for the overlay defect; however, when the ratio is higher than approximately 20% of the nominal value, a different defect type is formed in the SOG layer due to the inverse ARDE effect that propagates downstream to the SiO2 layer.

Background: Natural physical phenomena occurring at length scales of a few nm produces variation in many aspects of the EUV photoresist relief image: edge roughness, width roughness, feature-tofeature variability, etc. 1,2,3,4. But the most damaging of these variations are stochastic or probabilistic printing failures 5, 6. Stochastic or probabilistic failures are highly random with respect to count and location and occur on wafers at spectra of unknown frequencies. Examples of these are space bridging, line breaking, missing and merging holes. Each has potential to damage or destroy the device, reducing yield 6, 10. Each has potential to damage or destroy the device, reducing yield 6, 10. The phenomena likely originates during exposure where quantized light and matter interact1 . EUV lithography is especially problematic since the uncertainty of energy absorbed by a volume of resist is much greater at 13.5 nm vs. 248 nm and 193 nm. Methods: In this paper, we use highly accelerated rigorous 3D probabilistic computational lithography and inspection to scan an entire EUV advanced node layout, predicting the location, type and probability of stochastic printing failures.

Optical lithography is rapidly becoming very complex. As the limits of resolution are pushed to achieve feature sizes on the order of the wavelength of light or smaller, many phenomena must be understood. Technology innovation to extend optical lithography is also introducing many implementation options that must be assessed. Together, the increased concern for physical effects and the introduction of innovations have greatly increased the number of parameters whose effects must be characterized and balanced. Modeling offers a solid foundation for efficient characterization and a way to systematically quantify relationships and quickly investigate new innovations. The ultimate test is, of course, producing the desired features on product wafers. Yet a little time spent in understanding the models or in making a few simulation runs at a computer terminal can make working in the fabrication facility much more effective. It is also true that observational feedback from the fabrication facility can make modeling and simulation much more effective. This chapter is designed to provide information about modeling and simulation at four distinct levels. It begins with an overview of the phases and nature of modeling and simulation. Then the underlying basic physical models and phenomena of optical imaging, substrate interactions, and resist dissolution are considered. The usefulness of modeling and simulation in concert with conventional characterization methods for determining the practical performance of lithography is then illustrated. Uses of modeling and simulation in assessing technology innovation in materials, exposure tools, masks, etc., are considered. Finally, a summary of available simulators is provided.

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

In this publication the authors have investigated both theoretically and experimentally the link between line edge roughness, target noise and overlay mark fidelity. Based on previous work(i), a model is presented to explain how any given edge of a printed feature could have a mean position that varies stochastically (i.e., randomly, following a normal distribution) due to lithography stochastic variation. The amount of variation is a function of the magnitude of the LER (more accurately, all the statistical properties of the LER) and the length of the feature edge. These quantities have been analytically linked to provide an estimate for the minimum line length for both optical and e-beam based overlay metrology. The model results have been compared with experimental results from wafers manufactured at IMEC on both EUV and ArF lithographic processes developed for the 10 nm node, with extrapolation to the 5 nm node.

In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion - that of process resilience.

We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

We present a metrology target design (MTD) framework based on co-optimizing lithography and metrology performance. The overlay metrology performance is strongly related to the target design and optimizing the target under different process variations in a high NA optical lithography tool and measurement conditions in a metrology tool becomes critical for sub-20nm nodes. The lithography performance can be quantified by device matching and printability metrics, while accuracy and precision metrics are used to quantify the metrology performance. Based on using these metrics, we demonstrate how the optimized target can improve target printability while maintaining the good metrology performance for rotated dipole illumination used for printing a sub-100nm diagonal feature in a memory active layer. The remaining challenges and the existing tradeoff between metrology and lithography performance are explored with the metrology target designer’s perspective. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.

Computer simulation of lithographic performance, including resist CD, film thickness, sidewall angle and profile has been extensively studied during the past three decades. Lithography simulation has been widely adopted as an enabling technology for high-volume chip manufacturing. However, measurement artifacts arising from CD-SEM metrology are typically ignored in simulation, due to the difficulty of accurately modeling the effect of the CD-SEM at acceptable computational speed. In this paper, we demonstrate how CD measurements can be improved by including a fast, compact CD-SEM model. For example, the variation in effective resist metrology height along contour lines extracted from a simulated CD-SEM image is characterized for a range of structures through focus. We also demonstrate how SEM settings affect the shape of extracted SEM contour and metrology height at contour edge. The Edge Placement Error (EPE) caused by SEM artifact is carefully studied.

Background: Clinicians who assess and treat patients for scoliosis typically use parameters that are all visible from the posterior view. Radiographs assess the internal spinal deformity, but do not directly evaluate body shape, either posterior or anterior. This is problematic, as the patient is most concerned about the way they appear in the mirror. An objective set of anterior measurements is needed to help quantify the anterior asymmetry that is present in scoliosis.Methods: The design of this system of assessment was developed as a consensus of thinking from four points of view. A spine surgeon provided the musculoskeletal structural perspective. A plastic surgeon specializing in breast reconstruction provided the aesthetic and soft tissue perspective. A surface topography researcher provided the imaging perspective, and a scoliosis patient provided the self-perception and emotional perspective. Using an iterative process, a series of potential measurement parameters using surface topography measurements were considered, debated, and ultimately selected to be part of a system of measurement that provides an overall assessment of anterior trunk asymmetry.Results: An anterior surface topography scan in the relaxed, standing position was taken of the scoliosis patient. The computer provides a 3D topographical model that is used to complete measurements that can be combined to achieve an Anterior Aesthetic Deformity Score. Shoulder parameters, including shoulder height difference and shoulder slope difference, make up 40 % of the total score. Breast asymmetry, including nipple height difference and sternal notch-to-nipple distance, make up 30 % of the total score. Waist asymmetry makes up the final 30 % of the score, providing an objective and quantifiable measure of anterior trunk deformity.Conclusions: These measurements provide an objective, systematic evaluation of anterior trunk asymmetry that can be used in the assessment of patients with scoliosis. Clinical research should now be done to validate this system and show that it is reproducible in a variety of settings and patients.

We present a cost-effective focus monitoring technique based on the illumination and the target co-optimization. An advanced immersion scanner can provide the freeform illumination that enables the use of any kind of custom source shape by using a programmable array of thousands of individually adjustable micro-mirrors. Therefore, one can produce non-telecentricity using the asymmetric illumination in the scanner with the optimized focus target on the cost-effective binary OMOG mask. Then, the scanner focus variations directly translate into easily measurable overlay shifts in the printed pattern with high sensitivity (ΔShift/Δfocus = 60nm/100nm). In addition, the capability of using the freeform illumination allows us to computationally co-optimize the source and the focus target, simultaneously, generating not only vertical or horizontal shifts, but also introducing diagonal pattern shifts. The focus-induced pattern shifts can be accurately measured by standard wafer metrology tools such as CD-SEM and overlay metrology tools.

We present a framework to analyze the performance of optical imaging in a hyper numerical aperture (NA) immersion lithography scanner. We investigate the method to quantify imaging performance by computing upperand lower-bounds on the threshold normalized image log-slope (NILS) and the depth of focus (DOF) in conjunction with the traditional image quality metrics such as the mask error enhancement factor (MEEF) and the linearity for various different pitches and line to space (LS) duty cycles. The effects of the interaction between the light illumination and the feature size are extensively characterized based on the aerial image (AI) behavior in particular for the extreme dipole illumination that is one of the commonly used off-axis illuminations for sub-100nm logic and memory devices, providing resolution near the physical limit of an optical single patterning step. The proposed aerial imaging-based DOF bounds are compared to the results obtained from an experimentally calibrated resist model, and we observed good agreement. In general, the extreme dipole illumination is only optimal for a single particular pitch, therefore understanding the through-pitch imaging performance bound, which depends on the illumination shape, pattern size, and process conditions, is critically important. We find that overall imaging performance varies depending upon the number of diffracted beams passing through the scanner optics. An even number of beams provides very different trends compared to the results from an odd-number of beams. This significant non-linear behavior occurs in certain pitch regions corresponding to 3 beam interference imaging. In this region the imaging performance and the pattern printability become extremely sensitive to the LS duty cycle. In addition, there is a notable tradeoff between the DOF and the NILS that is observed in the problematic 3-beam region and this tradeoff eventually affects the achievable process window (PW). Given the practical real world constraints such as the design rules and target design restrictions, computing upper- and lower-bounds of the through-pitch DOF and NILS will be especially useful for both lithographers and metrology target designers in understanding this complex behavior, as well as helping in the design of optimal targets used for applications including alignment, overlay control, and process control in high volume semiconductor manufacturing.

Feedback control of overlay errors to the scanner is a well-established technique in semiconductor manufacturing [1]. Typically, overlay errors are measured, and then modeled by least-squares fitting to an overlay model. Overlay models are typically Cartesian polynomial functions of position within the wafer (Xw, Yw), and of position within the field (Xf, Yf). The coefficients from the data fit can then be fed back to the scanner to reduce overlay errors in future wafer exposures, usually via a historically weighted moving average. In this study, rather than using the standard Cartesian formulation, we examine overlay models using Zernike polynomials to represent the wafer-level terms, and Legendre polynomials to represent the field-level terms. Zernike and Legendre polynomials can be selected to have the same fitting capability as standard polynomials (e.g., second order in X and Y, or third order in X and Y). However, Zernike polynomials have the additional property of being orthogonal over the unit disk, which makes them appropriate for the wafer-level model, and Legendre polynomials are orthogonal over the unit square, which makes them appropriate for the field-level model. We show several benefits of Zernike/Legendre-based models in this investigation in an Advanced Process Control (APC) simulation using highly-sampled fab data. First, the orthogonality property leads to less interaction between the terms, which makes the lot-to-lot variation in the fitted coefficients smaller than when standard polynomials are used. Second, the fitting process itself is less coupled – fitting to a lower-order model, and then fitting the residuals to a higher order model gives very similar results as fitting all of the terms at once. This property makes fitting techniques such as dual pass or cascading [2] unnecessary, and greatly simplifies the options available for the model recipe. The Zernike/Legendre basis gives overlay performance (mean plus 3 sigma of the residuals) that is the same as standard Cartesian polynomials, but with stability similar to the dual-pass recipe. Finally, we show that these properties are intimately tied to the sample plan on the wafer, and that the model type and sampling must be considered at the same time to demonstrate the benefits of an orthogonal set of functions.

Directed Self-Assembly (DSA) is one of the leading candidates for next generation patterning in IC manufacturing. With the continued delay of EUV and the increasing costs of evermore complex multi-patterning techniques, DSA has the potential to produce small, well-defined features on a tight pitch. The graphoepitaxy DSA approach can be used to form single or multiple uniform contact holes (cylinders) well below the resolution limit of the optical exposure tool in a pre-pattern template. The utility of these patterns in the semiconductor manufacturing process is dependent on the capability of the process to control the size, edge roughness and placement of these DSA structures in the presence of reasonable levels of variation in the DSA material, the processing of that material and the pre-pattern template.In this study, a 3-D Self-Consistent Field Theory (SCFT) model has been developed to describe the behavior of such DSA systems. The utility of the simulator to describe actual physical behavior is explored, by fine tuning the SCFT model input parameters against experimental data for certain pre-pattern configurations and then evaluating the model predictions for other separate pre-pattern shapes. Two separate calibration studies are presented, one with 2-D guide patterns, in which multiple holes are positioned in a 2-D irregular array, and the other with 1-D structures, where the holes are distributed along one direction only. Pattern contours are extracted from CD-SEM images. A metric that measures the CD and placement is used to evaluate the modeled contours against the experimental contours.

Scanning Electron Microscopy (SEM) is widely used to measure Critical Dimensions (CD) in semiconductor lithography processes. Correlation between the CD-SEM metrology and target profile has drawing attention from metrology community [1]. In this paper, we use a recently developed CD-SEM simulator [2-3] to investigate some artifacts of SEM metrology. The simulation consists of two parts. First part is a stochastic resist modeling for lines and spaces through pitch, exposure dose and focus. Second part is CD-SEM simulation. Both CD and LWR extracted from experimental CD-SEM images were used to train the SEM model. Two types of artifacts were found to be metrology dependent: the first artifact is that a CD-SEM measures CD at various heights across pitch for the same SEM threshold. The second artifact is a misleading CD measurement for trenches not fully developed. By overlapping the CD-SEM simulation with 3D lithography simulation, correlation between CD-SEM metrology and target 3D profile is studied. Finally, a Process Window (PW) analysis based on both experiment and simulation is presented, using the simulated features and SEM images to correct the experimental PW.