This paper presents the system and circuit design of a compact radio frequency (RF)-powered 2.4-GHz CMOS transmitter (TX) to be used for autonomous wireless sensor nodes (WSNs). The proposed TX utilizes the received dedicated RF signal for both energy harvesting as well as frequency synthesis. A TX RF carrier is derived from the received RF signal by means of a delay locked loop and XOR-based frequency multiplier. The 50- $\Omega $ load is subsequently driven by a tuned switching RF power amplifier (PA) with 25% duty cycle input for high global efficiency. The design is fabricated in 40-nm CMOS technology and occupies a die area of 0.16 mm2. Experimental results show a rectifier with 36.83% peak efficiency and power management circuit with 120-nA current consumption that enables a low start-up power of −18.4 dBm. The TX outputs a continuous 2.44-GHz RF signal at −2.57 dBm with 36.5% PA drain efficiency and 23.9% global efficiency from a 915-MHz RF input and supports ON–OFF keying modulation.

Energy scavenged Wireless Sensor Nodes (WSNs) usually require a small output power ( 0 dBm) due to their short-range application and limited power budget. This makes the RF Power Amplifier (PA) design differ from conventional PAs as the output power becomes comparable to the PA driver's power consumption. In this letter, a 2.4 GHz tuned switching PA and driver is proposed with an on-chip duty cycle calibration loop to enhance efficiency. A prototype is fabricated in 40 nm CMOS technology and supports On-Off keying (OOK). Measurements show a global efficiency of 40% when delivering -5 dBm to a 50 Ω load.

Energy scavenged Wireless Sensor Nodes (WSNs) usually require a small output power (<0 dBm) due to their short-range application and limited power budget. This makes the RF Power Amplifier (PA) design differ from conventional PAs as the output power becomes comparable to the PA driver's power consumption. In this letter, a 2.4 GHz tuned switching PA and driver is proposed with an on-chip duty cycle calibration loop to enhance efficiency. A prototype is fabricated in 40 nm CMOS technology and supports On-Off keying (OOK). Measurements show a global efficiency of 40% when delivering -5 dBm to a 50 Omega load.

The aim of this brief is to point out the importance of codesigning electrically short antenna-electronics interfaces as a way to improve the system performance. This can be achieved if both the antenna and electronic circuit designer have a common optimization target. In this brief, the codesign principles are presented for antenna systems in the receiving mode, which includes reception of wireless information and wireless power. A general interface analysis is carried out, suggesting that the choice of interface impedance plays a crucial role in the optimization procedure and depends on the preferred signal quantity of the electronic circuit. This allows to effectively improve design criteria such as noise figure, power efficiency and sensitivity without increasing the power consumption. Finally, two examples are treated to demonstrate the antenna-electronics codesign for the reception of wireless information (low-noise amplifier) and wireless power (radio-frequency energy harvesting).

Energy scavenged Wireless Sensor Nodes (WSNs) usually require a small output power ( 0 dBm) due to their short-range application and limited power budget. This makes the RF Power Amplifier (PA) design differ from conventional PAs as the output power becomes comparable to the PA driver's power consumption. In this letter, a 2.4 GHz tuned switching PA and driver is proposed with an on-chip duty cycle calibration loop to enhance efficiency. A prototype is fabricated in 40 nm CMOS technology and supports On-Off keying (OOK). Measurements show a global efficiency of 40% when delivering -5 dBm to a 50 Ω load.

Radio frequency energy harvesting (RFEH) is an energy conversion technique employed for converting energy from the electromagnetic (EM) field into the electrical domain (i.e., into voltages and currents). In particular, RFEH is a very appealing solution for use in body area networks as it allows low-power sensors and systems to be wirelessly powered in various application scenarios. Extracting energy from RF sources sets a challenging task to designers and researchers as they find themselves at the interface between the electromagnetic fields and the electronic circuitry. Therefore, knowledge from both domains is required in order to design a high-performance RF energy harvester. In this chapter, the fundamentals, limitations, trade-offs, and challenges of RF energy harvesting are introduced both on system and circuit levels. Several design techniques, such as passive voltage boosting and impedance matching, are presented. State-of-the-art solutions are presented, their advantages and limitations are described, and their figure-of-merit discussed. The rectifier non-linear impedance and performance with respect to frequency, aspect ratio, threshold voltage, loading conditions, and input power variations are discussed. Moreover, the impedance variation introduced by (flexible) antennas for wearable sensors is presented and a technique to overcome the effects of impedance changes is presented. The choice of the antenna-rectifier interface impedance is discussed as it plays a crucial role in the harvester sensitivity and power conversion efficiency optimization. In the last subsection an example of an RFEH design is furnished, starting from the system level specification requirements of a wearable sensor. Finally, a co-design is described to optimize the antenna-rectifier interface.

In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a-27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.

This paper presents a self-calibrating RF energy harvester capable of harvesting at lower input power levels than current state-of-the-art RF harvesters. A 5 stage cross-connected bridge rectifier is brought at resonance with a high-Q loop antenna by means of a 7-bit binary weighted capacitor bank. A control loop compensates any variation in the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. The rectifier and capacitor bank have been implemented in standard 90nm CMOS technology, includes ESD protection and are integrated on the antenna. Measurements in an anechoic chamber at 868 MHz show a -26.3 dBm sensitivity for 1V output and 25 meter range for a 1.78 W RF source in an office corridor. The maximum power efficiency of the complete harvester is 31.5%.

The main design challenge for current state-of-the-art RF energy harvesters is to improve the sensitivity (wireless range), efficiency and robustness simultaneously. Generating a sufficiently large voltage to activate the rectifier with a few μW of power is the first concern as MOS transistors inherently are voltage-controlled devices. To address these issues, a design methodology is described for the co-design and integration of a CMOS rectifier and small loop antenna for highly sensitive RF energy harvesters. It is shown that the choice of antenna-rectifier interface impedance plays a crucial role in this optimization. Following this methodology, a 5 stage cross-connected bridge rectifier is designed that is brought at resonance with a highQ loop antenna by means of a 7-bit binary weighted capacitor bank. A feedback controlled voltage boosting and tuning network compensates any impedance variation in the interface that may occur in a realistic environment, making the RF energy harvester very robust while fully benefiting from the passive voltage boost obtained from the high-Q network. Subsequently, a small loop antenna is designed which meets the specific requirements obtained from the rectifier impedance. The rectifier and capacitor bank have been implemented in standard 90 nm CMOS technology, includes ESD protection and are integrated on the antenna. Measurements in an anechoic chamber at 868MHz show a −27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78W RF source in an office corridor. The maximum power conversion efficiency equals 40% at −17 dBm.

The full equivalence of the Thévenin and Norton Kirchhoff circuits of an $N$-port receiving antenna is discussed.

This paper presents the design of a robust and large range RF energy harvester with a control loop. The harvester is based on an optimally mismatched antenna-rectifier interface that offers a large passive voltage boost to increase the sensitivity of the energy harvester while still extracting energy from the antenna. A control loop is proposed that maximizes the voltage on the storage capacitor by keeping the rectifier at resonance during charging continuously. The basic principle of this loop has been implemented and verified with simulations. The loop is able to optimize the antenna-electronics interface for a ±33% change in antenna reactance. A comparison with state-of-the-art RF energy harvesters shows major improvements in rectified output voltage at power levels lower than -25 dBm.

The design of a MOS-only pulse generator for sub-GHz Ultra-Wideband (UWB) biomedical communication is presented. The oscillator based pulse generator is capable of generating Binary Phase Shift Keying (BPSK) modulated pulses and is tunable in both frequency and output power. A varactor biasing circuit is developed that keeps the varactor bias voltage constant during oscillator startup and shutdown. The pulse occupies a bandwidth of 550 MHz. The center frequency can be controlled from 0.53 to 1.05 GHz and the digital gain control offers a 13.5 dB tuning range. For a 2.5 V supply and 1 MHz Pulse Repetition Frequency (PRF), the average power consumption ranges from 30 μW to 150 μW, depending on the pulse power controlled by the digital gain. The circuit performance is very robust over process corners, device mismatch and antenna reactance variations.

This paper proposes the use of sub-GHz impulse radio Ultra-Wideband (UWB) communication for implantable medical devices. This new concept can offer a more reliable, safer and lower power consuming wireless link compared to other biomedical communications today. An operating frequency below 1 GHz is required to minimize the dielectric absorption of the human tissue and simultaneously allows for low power electronics. Investigating the antenna-electronics interface show that a current driven antenna results in the most reliable signal transfer. This interface is not bounded to the conventional 50 Ω interface.