The suppression of the large resonance peak that may appear due to the equivalent parallel circuit between the package capacitance and PCB inductance is discussed. Such resonance may be amplified if the decoupling capacitors are not appropriately selected. The relevant parameters involved in the PDN design and a feasible solution strategy are presented based on the identification of a simplified equivalent circuit that is able to replicate the resonant behavior. The optimization of the relevant parameters of such circuit are able to suggest the best strategy for identifying the decoupling capacitors with appropriate values of parasitic inductance and resistance.

System-level power distribution network (PDN) impedance optimization utilizing the zeros of the decoupling capacitors (decaps) is discussed in this paper. An example of a practical PDN application is proposed to validate the poles and zeros algorithm (P&Z) presented. The system-level PDN is with the printed circuit board (PCB), package (PKG), and chip, as well as the low-frequency decaps on the PCB and the on-PKG decoupling capacitors. The PDN optimization results are compared with those from the genetic algorithm (GA) to show the reasonableness and validity of the P&Z algorithm.

A physics-based modeling methodology for determining the transient current flow path in multi-layer PI designs is given in this paper using a commercial board with a complicated structure as an example. Board structure analysis is done first to provide a physical basis of post-layout analytical and equivalent circuit modeling. A match of the PDN impedance between commercial tool simulation, post-layout analytical calculation, and the physics-based equivalent circuit modeling was achieved to support the model for the transient simulation. By analyzing the current response in all the vias, a clear representation of transient current flow across all via segments can be given layer-by-layer. The maximum current density in vertical vias can also be extracted in this process, providing a reference for preventing transient overcurrent design.

Channel loss, crosstalk, power noise, reflections and phase-locked loop design can lead to significant degradation of high-speed signal reference clocks. This paper describes a methodology to ensure that the stringent reference clock jitter and phase noise specifications for PCIe Gen5 and subsequent standards are met for a system reference clock that crosses one or more printed circuit boards. The authors investigate real time oscilloscope and phase noise analyzer analysis methods utilizing reference designs, evaluation test vehicles, and custom clock hardware. The methods described investigate both time and frequency domain assessment, their respective advantages and disadvantages, and the precautions the signal integrity engineer must be aware of when utilizing each method to verify reference clock stability. The impact of reference clock architecture and spread spectrum clocking on the margin of PCIe Gen5 systems is important to characterize, and the test vehicles designed for this paper will characterize this important detail as future work. Finally, the analysis presented in this paper includes examples of specialized measurement techniques including use of linear amplifiers, cross-correlation and baluns combined with and without twin-axial passive probes.

An optimization routine is applied for the decoupling capacitor placement on Power Distribution Networks to identify the limit beyond which the placement of additional decaps is no longer effective, thus leading to wasting layout area and components, and to a cost increase. A specific test example from a real design is used together with the required target impedance and frequency band of interest for the PDN design. The effectiveness of the decap placement while selecting different layers of the stack-up, and while moving the upper limit of the PDN design band is analyzed. Such analysis leads to helpful insights based on the progression of the input impedance during the optimization process, and to develop useful guidelines for avoiding over-design of the PDN.

With increasingly stringent requirements for lower voltage supply, and higher density in PCB (Printed Circuit) PDN (Power Distribution Network) design, power integrity has an increasingly important role in PCB design. The PI performance of the PCB design must meet requirements, or modification and trial-and-error are necessary to ensure the target impedance is satisfied. Lots of design practices and commercial tools are utilized to aid PI designers, e.g., developing a suitable stack-up, saving cost while placing enough decoupling capacitors, best layout for IC pins and so on. It is essential in the PCB PDN design to place as fewer decoupling capacitors as possible to achieve target impedance and voltage ripple goals while saving cost. In this paper, the influence from the types of decoupling capacitor and stack-up is considered. The variety of decoupling capacitors contributes to the objective of reaching the target with minimum number of decoupling capacitors.

A method to model, measure, and characterize a high-transient current in an electrical packaging solution is described herein. These methods help overcome the challenge of generating model to hardware correlation in high current applications. A specialized test platform is developed and used to characterize current density in test hardware. The measurements are used to characterize a custom power distribution network and verify validity of current density predictions. This data is critical in high-current applications for finding and measuring current density through plane pinch points that can cause early failures in the field due to electromigration and delamination.

This paper presents a cost-effective method using 3D printing technology to reduce the parasitic losses when probing a channel with a logic analyzer compared to traditional methods. The method is demonstrated on a 16 Gb/s PCIe Gen4 channel, taking advantage of the physically accessible SMT AC decoupling capacitors through a custom fixture to contact the signals of the high-speed serial (HSS) channel. Channel topology, length and transceiver compensation, and sophisticated equalization has increased link frequency dramatically at the cost of complexity. This renders traditional debug activities using an oscilloscope to be of very limited value in the characterization and verification of the link. The protocol-awareness of HSS links, including the use of retimers, makes the use of a logic analyzer necessary. While a logic analyzer fills the need for protocol analysis and timing data to debug link errors that would be undetected by traditional oscilloscope efforts, the fixturing to contact the signals introduces an electrical loading in the channel. As data rates continue to increase, the loading becomes increasingly severe. The commonly available probe connectors for logic analyzers are physically large, require substantial board real estate, and consume a notable percentage of channel margin due to its parasitic losses. With the proposed method, HSS channels can be analyzed during link operation and link training. Prototype parts can be analyzed and, with fore-thought and planning, even failure analysis of customer-failing parts can be investigated. The fixturing is affordable, compact, and configurable using 3D printing technology promising continued use as HSS data rates continue to increase.

The design for high-speed channels within electronic packaging traditionally focuses on interconnect and packaging solutions pertaining primarily to the signal conductor portion of a transmission line. However, the overall construct and path between driver and receiver includes not only the signal, but also the image return path, requiring the Signal Integrity engineer to pay close attention to the round-trip current path. Traditionally, this means that discontinuities in the ground return path are avoided at all cost. This paper will investigate deviations from this traditional mode of operation by exploring an application requiring intentionally designed traces over ground discontinuities. Additionally, the authors explore modeled and measured results obtained from constructs posed as alternatives to discontinuous ground transmission lines.