E-business organizations commonly trade services together with quality of service (QoS) guarantees that are often dynamically agreed upon prior to service provisioning. Violating agreed QoS levels incurs penalties and hence service providers agree to QoS requests only after assessing the resource availability. Thus the system should, in addition to providing the services: (i) monitor resource availability, (ii) assess the affordability of a requested QoS level, and (iii) adapt autonomically to QoS perturbations which might undermine any assumptions made during assessment. This paper will focus on building such a system for reliably multicasting messages of arbitrary size over a loss-prone network of arbitrary topology such as the Internet. The QoS metrics of interest will be reliability, latency and relative latency. We meet the objectives (i)-(iii) by describing a network monitoring scheme, developing two multicast protocols, and by analytically estimating the achievable latencies and reliability in terms of controllable protocol parameters. Protocol development involves extending in two distinct ways an existing QoS-adaptive protocol designed for a single packet. Analytical estimation makes use of experimentally justified approximations and their impact is evaluated through simulations. As the protocol extension approaches are complementary in nature, so are the application contexts they are found best suited to; e.g., one is suited to small messages while the other to large messages

This paper presents the techniques being developed to design a high speed PostScript rendering engine using virtual hardware. The problem of rendering PostScript is decomposed into a series of tasks which can be performed in sequence on one FPGA using virtual hardware.

Reconfigurable processor hybrids are becoming an accepted solution in the embedded systems domain, but have yet to gain acceptance in the general purpose workstation domain. One problem with current solutions is their lack of support for the dynamic workloads and resource demands of a general purpose workstation. In this paper we describe and demonstrate a reconfigurable processor architecture that lets the operating system dynamically share the Field Programmable Logic (FPL) resource between a set of applications without the management overheads negating the benefit of having the extra resource.

The Proteus Architecture proposed a general purpose microprocessor with reconfigurable function units. The ProteanARM represents an ARM-based realisation of this concept. This paper describes the initial details of the ProteanARM architecture and demonstrates some performance benefits gained through the use of custom function units. Our examples show a promising performance increase compared to a standard ARMprocessor, with reconfiguration costs being quickly amortised.

The Dagstuhl Seminar on Dynamically Reconfigurable Architectures brought together 42 participants from 11 different countries. As with its predecessor seminar held in 1998, the participants came from three distinct communities, concerned with: • field programmable gate arrays for fast and flexible configurable computing, and the associated design tools; and • computational models of, and designing efficient algorithms for, processor arrays with reconfigurable bus systems; • optoelectronic systems for communication with very high bandwidth. A main aim of the seminar was to encourage cross-fertilisation between these communities, to work towards a new understanding of dynamically reconfigurable architectures and their possibilities. Some of the specific questions addressed by the seminar were: • What are shared characteristics of, and possible interfaces between, machine-based computational models and circuit-based computational models? • How will current ”ASIC replacement” device architectures evolve to be genuine ”computational component” device architectures? • What are appropriate system-level architectures for systems composed of processors, configurable logic and memory, and how might these be implemented at chip level? • What overall computational models are best to evaluate alternative system-level architectures? • Which aspects of current hardware and software design practice are, and are not, relevant to the design of ”soft” circuitry and ”hard” programs? • What are appropriate new design processes, and supporting tools, for systems composed of a mixture of circuit and program, implemented in hard and soft manners?

Traditional operating systems present fixed, high-level abstractions to application developers and users. These are part of standard APIs, such as POSIX or X/OPEN, which are typically implemented as a thin library layer on top of monolithic kernels. Recent efforts in operating system research, however, have focussed on providing more flexibility and new functionality to applications by lowering the abstraction level to a minimal kernel interface. Higher-level abstractions are provided through user-level servers or, more recently, through shared libraries. These library based operating systems allow the design and implementation of arbitrary high-level abstractions as user-level shared libraries on top of a minimal kernel interface. Nemesisis a library based operating system which offers genuine support for multi-media data stream types by providing Quality of Service guarantees for all shared resources in the system. In Nemesis, the libraries implementing the high level abstractions are carefully designed to avoid interactions between different processes for shared state. Abstractions which rely on traditional stateful APIs are handled using library componets calledpersonalities, described in (Neugebauer & Black 1998). This deliverable report describes the design and implementation of a personality offering Unix-like functionality for the Nemesis operating system. This effort was motivated on two grounds: first, to research the techniques and feasibility of providing such functionality in a single address space system such as Nemesis, and second, by the desire to take advantage of the vast amount of existing application code available for Unix systems.

This paper describes the starting position for research beginning at the Department of Computing Science, University of Glasgow. The research will investigate a novel microprocessor design incorporating reconfigurable logic in its ALU, allowing the processor’s function units to be customised to suit the currently running application. We argue that this architecture will provide a performance gain for a wide range of applications without additional programmer effort. The paper gives some background information into similar research, argues the benefits of this idea compared to current research, and lists some of the questions that need to be answered to make this idea a reality. We end by specifying the initial work plan for the project.

This paper presents the techniques being developed to design a high speed PostScript rendering engine using virtual hardware. The problem of rendering PostScript for high quality colour correct printed output is decomposed into a series of tasks which can be performed in sequence on one FPGA, making this application very suitable for implementation with virtual hardware. The virtual hardware solution promises superior performance and much lower cost than existing PostScript rendering systems.

This document gives a brief explanation of the design and implementation of SWARM — the Soft- ware ARM. It explains what SWARM is, and what it isn't, along with the design philosophy.

This document outlines the network measurement layer designed to support the QoS Group Communication system. Together with deliverable D8 - QoS-Enabled Group Communication provides a full description of the TAPAS Group Communication facility. This document is structured so as to discuss the system's requirements first, after which it provides a brief high level look at how the system is designed and concludes with a few words on the integration issues with the rest of the Group Communication system. Introduction In deliverable D8 (QoS-Enabled Group Communication) (diferdinandoD8) we introduced the Group Communication (GC) system designed for the TAPAS project. This system provides users with probabilistic delay guarantees over the entire group. In order to be able to provide this guarantee, the communication service needs to be aware of the current state of the network behaviour for the group, as described in (diferdinando04), in order to be able to carry out access control. The group communication system will be then capable of deciding whether accept or not a communication request, with a given delay and probability bounds, only if it knows whether the network conditions will be able to support the service level requested. This document describes the Network Measurement System (NMS) designed to support the TAPAS GC protocol. It extends the TAPAS deliverable D8 so as to complete description of the GC System. Section 2 describes both functional and non-functional requirements for the NMS. Design is described in Section 3, whilst integration with the rest of the GC system is described in Section 4.