Well-known techniques exist for proving the soundness of subtyping relations with respect to type safety. However, completeness has not been treated with widely applicable techniques, as far as we are aware. This paper develops some techniques for stating and proving that a subtyping relation is complete with respect to type safety and applies the techniques to the study of iso-recursive subtyping. The common subtyping rules for iso-recursive types—the “Amber rules”—are shown to be incomplete with respect to type safety. That is, there exist iso-recursive types 1 and 2 such that 1 can safely be considered a subtype of 2, but 1 2 is not derivable with the Amber rules. This paper defines new, algorithmic rules for subtyping isorecursive types and proves that the rules are sound and complete with respect to type safety.

Reversible computation differs from traditional computation in that it preserves information while manipulating it. This new design paradigm has very attractive thermodynamic consequences and holds many applications in current and emerging technologies. Modern computers can reduce power consumption by taking advantage of reversibility, and quantum computers operate reversibly. Researchers have already proposed reversible designs of many common arithmetic and logical units, including adders, multipliers, shifters, and even registers. Very little focused work has been done specifically on reversible encoder/decoder design. In this paper we propose a novel reversible encoder/decoder design and analyze it in terms of its quantum cost, garbage outputs, constant inputs, and quantum delay.

The study of reversible circuits holds great promise for emerging technologies. Reversible circuits offer the possibility for great reductions in power consumption, and quantum computers will require logically reversible digital circuits. Many different reversible implementations of logical and arithmetic units have been proposed in the literature, but very few reversible floating-point designs exist. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition to be the most oft used floating-point operation. In this paper we present for the first time a reversible floating-point adder that closely follows the IEEE754 specification for binary floating-point arithmetic. Our design requires reversible designs of a controlled swap unit, a subtracter, an alignment unit, signed integer representation conversion units, an integer adder, a normalization unit, and a rounding unit. We analyze these major components in terms of quantum cost, garbage outputs, and constant inputs.

Reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing, and other emerging computing technologies. Further, floating point multiplication is one of the major operations in image and digital signal processing applications. The single precision floating-point multiplier requires the design of efficient 24×24 bit integer multiplier. In this work, we propose a new reversible design of single precision floating point multiplier based on operand decomposition approach. To design the reversible 24×24 (A×B) bit multiplier (assume A and B are of 24 bits each), the operands are decomposed into three partitions of 8 bits each. Thus, the 24×24 bit reversible multiplication is performed through nine reversible 8×8 bit Wallace tree multipliers, whose outputs are then summed. We propose a new reversible design of the 8×8 bit Wallace tree multiplier that has been optimized in terms of quantum cost, delay, and number of garbage outputs. Wallace tree multiplication consists of three conceptual stages: Partial product generation, partial product compression using 4:2 compressors, full adders, and half adders, and then the final addition stage to generate the product. In this work we perform optimization at each of these three stages. For the first stage, we have proposed a new generalized reversible partial product generation circuitry. For the second stage we have proposed a new reversible 4:2 compressor design for use in the compression tree. Finally, for the summation stage we have carefully chosen and arranged the reversible half adders and full adders in such a way to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. We have also illustrated the reversible design of 24×24 bit multiplier using the proposed 8×8 bit reversible Wallace tree multiplier.