This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is ±0.005 dB/°C from −15°C to 85 °C at 17.7–19.2 GHz, while the counterpart without temperature compensation is −0.1 dB/°C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.2–4.1-dB noise figure (NF), and a −27.4-dBm input 1-dB gain compression point (IP $_{\mathrm {1\,dB}}$ ) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <1.5° root-mean-square (rms) phase error, and a < 0.22-dB rms amplitude error. The chip occupies $4.65\times2.77$ mm2 area with pads, equivalent to 1.61 mm2 per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.

This letter presents a 26–34.5-GHz power amplifier (PA) fabricated in 65-nm bulk CMOS with a core area of 0.338 mm 2 . To reduce the mismatch in the conversion between single-ended and differential signals, the symmetry of the baluns is analyzed in detail. To achieve a broadband operation, a wideband source impedance matching network is introduced. The measured small signal gain is 25.1 dB, and the proposed PA achieves 21.6-dBm saturated output power ( $P_{\mathrm {sat}}$ ) with 30.4% peak power-added efficiency (PAE) as well as OP 1 dB of 20.4 dBm with 29.4% PAE at 29 GHz. The 1-dB bandwidth of $P_{\mathrm {sat}}$ is from 26 to 34.5 GHz.

This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm 2 core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7–6.6 dB at dc–28 GHz and the rms amplitude and phase errors of four measured chips are < 0.15 dB and <0.8°, respectively. The return loss is better than 12 dB for all the 128 attenuation states. To the best of our knowledge, this chip demonstrates the highest attenuation accuracy and minimum phase variation among silicon-based DSAs with a similar dynamic range.

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The π-type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm 2 core area and consumes negligible power.

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 to -5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 × 0.68 mm 2 area excluding pads and consumes 75 mW.

Under the condition of gain-phase errors, the existing methods only consider that the arrival angle strictly falls on the divided grid, which will pose limitation on the accuracy of the direction of arrival (DOA) estimation. In this paper, a new DOA estimation method based on sparse reconstruction is proposed, which applies the first-order Taylor expansion to modify the array output model under the condition of grid mismatch, and then uses the alternate optimization method to solve the non-convex optimization problem, obtaining the grid angle and bias angle. Compared with the existing methods, the proposed method improves the accuracy of the DOA estimation without requiring change of the grid spacing. This method also performs independent of array phase errors. Simulation results verify the effectiveness of the proposed method.

Disclosed in the present invention is a semiconductor package structure having a micro-isolation cavity, comprising a multi-channel or multi-module semiconductor chip, a heat conductive substrate, a fixing filler, metal solder balls, metal wiring layers, dielectric layers, and via holes. A groove slightly larger than the chip is formed on the heat conductive substrate, the chip is placed in the groove in a flip-chip manner and bonded with the heat conductive substrate, and a chip pad is connected to a laminated circuit board below the chip pad by means of the metal solder balls. The laminated circuit board is provided with multiple metal wiring layers, the metal wiring layers are isolated by the dielectric layers, and different metal wiring layers are interconnected using the via holes. The chip is divided into different areas depending on channels or modules, the metal solder balls are closely arranged on the peripheral boundary of each area, and the chip, the metal solder balls, and the laminated circuit board form a micro-isolation cavity structure capable of effectively reducing electromagnetic coupling between the channels or modules. According to the present invention, the package volume is reduced, the transmission loss of a signal on an interconnection line is reduced, the degree of isolation between the channels or modules of the chip is effectively improved, and the system performance is improved.

Phased arrays have demonstrated great potential in 5/6G communication, radar and sensor applications [1 -4]. To achieve excellent performance, phased arrays require lownoise and high-linearity front-ends [5]. Most importantly, arrays demand uniform performance from all elements for optimum receiving G/T value and transmission effective isotropic radiated power (EIRP) [6]. Figure 14.7.1 exemplifies it with an array whose antenna element has 3dBi uniform gain on one side and no radiation on the other side. When all elements in an 8×1 linear array with a λ/2 space have identical characteristics, the array presents a 19dBi gain in the normal direction. Any temperature change in the array can be decomposed into an absolute temperature change superposed with a relative temperature variation. When the absolute temperature increases, the frontend gain decreases by as much as -0.1dB/°C [1]. When there is non-uniform solar radiation or heat generation inside the array, the relative temperature variation may present a gradient or a parabolic distribution. Taking a 64×1 array as an example, when there is a gain/phase mismatch with an average value of 0.125dB/1.25° between adjacent elements in a parabolic distribution locating at the center of the array, the formed beam presents a 1.4dBi main-lobe reduction in the normal direction and an 11.9dBi side-lobe degradation, shown in Fig. 14.7.1. It also shows an active array receiver front-end highlighting all the temperature-sensitive blocks. Calibration can adjust temperature-dependent performances [7]. However, periodic calibration inevitably takes time overhead and prevents array systems from full-time operations. Digital background calibration allows systems to operate uninterrupted, but may induce antenna boresight instability due to abrupt gain/phase change. In contrast, analog background calibration like adaptive healing design can resolve the above issues [8]. In this paper, we present an adaptive analog temperature healing receiver front-end with ±0.005dB/°C gain variation from -15 to 85°C environment temperature for a 17.7-to-19.2GHz phased array.

This paper presents a 4-element 7.5-9 GHz phased array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. All the elements are fully-connected to each output beam using 32 phase shifters and 8 active combiners. The current-starving gm-based phase shifter with 6-bit phase resolution achieves <2° RMS phase error and <0.3 dB RMS gain error. The receiver demonstrates 20 dB gain, 3.6 dB noise figure (NF) and -19 dBm input 1-dB gain compression point (IP1dB) in 7.5-9 GHz band for each element. The chip occupies 5.42 × 3.62 mm2 area excluding pads and consumes 860 mW, equivalent to 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.

The invention relates to the technical field of integrated circuits. According to the on-chip variable gain temperature compensation amplifier, the bias voltage of a gain control transistor at different temperatures is changed, the ratio of forward gain to negative gain is adjusted, gain control is achieved in a positive and negative offset mode, and then the influence of on-chip temperature changes on device gain is compensated. The temperature compensation amplifier can cover the temperature change from-55 DEG C to 125 DEG C, and has the advantages of being large in gain range, high in compensation precision, low in power consumption, simple in structure and the like.

This paper presents a wideband balanced variable-gain low-noise amplifier (VGLNA) implemented in a 55-nm CMOS process. A frequency-selective non-foster gain equalization technique is proposed to compensate the gain variation of interstage dual-resonant tanks. This VGLNA leverages current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 dBm to -5 dBm. The LNA achieves a maximum power gain of 20.2 dB with ±0.5 dB gain variation and a minimum noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Owing to lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 mm × 0.68 mm area without pads and consumes 75 mW.

The invention discloses a hybrid broadband high-precision phase shifter integrated circuit, which belongs to the technical field of radio frequency integrated circuits, and is formed by cascading a pi-type L-C phase shift unit, a 22.5-degree switch-type phase shift unit, a 45-degree switch-type phase shift unit, a broadband quadrature signal generator, a quadrant selection unit and a transformer.The pi-type L-C phase shift unit is used for realizing 5.625-degree and 11.25-degree phase shift states; the two switch type phase shift units respectively realize 22.5-degree and 45-degree phase shift states, the quadrature signal generator is used for synthesizing a pair of quadrature differential signals, and the quadrant selection unit switches the positive and negative polarities of the quadrature signals through a switch to realize a 360-degree phase shift range. Compared with a traditional switch type phase shifter, the hybrid phase shifter has the advantages of being wide in band, lowin insertion loss, high in precision and the like.

The invention discloses a tightly-integrated chip packaging structure and a phased array radio frequency transceiving device formed by the tightly-integrated chip packaging structure. According to thepackaging structure, a plurality of chips with different production processes are integrated for design and packaging rather than independently designing of packaging of each chip and then board-level interconnection, and thus, the overall area is effectively reduced, the system integration is improved, the radio frequency performance is improved at the same time, the application cost is reduced,and the application of a plurality of chips with different production processes in the high-frequency satellite communication phased array becomes possible.

The invention relates to the technical field of integrated circuits, in particular to a broadband matching variable-gain low-noise amplifier. The gain of the low-noise amplifier can be flexibly adjusted through control of electric signals. Compared with a traditional low-noise amplifier, the low-noise amplifier has broadband impedance matching performance of the input end and the output end, and is suitable for occasions where broadband radio frequency receiving signals need to be processed.

The invention relates to the technical field of integrated circuits, in particular to an on-chip vector modulation phase shifter which generates phase shift within the range of 0-360 degrees through phase interpolation and has high phase shift precision and low phase shift error. Compared with a traditional vector modulation phase shifter, the power consumption of the vector modulation phase shifter can be reduced by 50%, and meanwhile the vector modulation phase shifter has the advantages of being small in area, low in cost, easy and convenient to design, capable of achieving broadband inputimpedance matching and the like.

The invention relates to the technical field of integrated circuits, in particular to an on-chip analog multi-beam phase-shifting synthesizer. The synthesizer can be applied to a phased array receiver, a single chip supports multi-beam combination, a complete connection architecture is adopted, each beam is generated by phase shift combination of received signals of all input channels. Compared with other multi-beam architectures, the phase-shifting synthesizer has higher combination gain, and meanwhile the signal-to-noise ratio and beam directivity of the receiver are improved. And the significance of multiple beams is that a single phased array system can track, measure, control and communicate multiple targets at the same time, and the application flexibility is higher.

The invention discloses an ultra-wideband low-phase error high-precision digital attenuator based on parallel capacitance compensation. A circuit is formed by cascading n attenuation units through inductance matching, and the n attenuation units adopt any one or more of a simplified T-shaped topological structure with parallel capacitance compensation, a bridging T-shaped topological structure with parallel capacitance compensation and a pi-shaped topological structure with parallel capacitance compensation. By adjusting the compensation capacitance value in each attenuation unit, the phases of different attenuation states can be adjusted to be almost consistent. The invention has the advantages of simple structure, high attenuation precision, wide working frequency band, small phase error, small insertion loss and small input/output voltage standing-wave ratio.

The invention discloses an ultra-wideband amplitude-phase compensation digital attenuator circuit, the circuit is formed by cascading n attenuation units through inductance matching, the n attenuationunits adopt any one or more of a simplified T-type circuit, a bridge-T topology with a compensation structure, and a pi-type topology with a phase compensation structure. The circuit is simple in topological structure, has a phase compensation structure, can realize an ultra-wideband working range, has the characteristics of low phase error, low insertion loss and high attenuation precision, andcan be produced on a large scale by adopting a microwave monolithic integrated circuit process technology.

Phased array radars are able to provide highly accurate airplane surveillance and tracking performance if they are properly calibrated. However, the ambient temperature variation and device aging could greatly deteriorate their performance. Currently, performing a calibration over a large-scale phased array with thousands of antennas is time-consuming. To facilitate the process, we propose a fast calibration method for phased arrays with omnidirectional radiation patterns based on the graph coloring theory. This method transforms the calibration problem into a coloring problem that aims at minimizing the number of used colors. By reusing the calibration time slots spatially, more than one omnidirectional antenna can perform calibration simultaneously. The simulation proves this method can prominently reduce total calibration time and recover the radiation pattern from amplitude and phase errors and noise. It is worth noting that the total calibration time consumed by the proposed method remains constant and is negligible compared with other calibration methods.

The invention discloses flexible phased array radar with a transient characteristic. The flexible phased array radar comprises a phased array radar assembly, an interconnecting wire, a flexible substrate, and a self-destroying structure. The self-destroying structure comprises a PAG/polymer structure. After the PAG/polymer structure is activated, acid solution would be generated to corrode the interconnecting wire or the phased array radar assembly. A rigid TR assembly is integrated on the flexible substrate with the transient characteristic. The flexible substrate has characteristics of deformable and good toughness, and volume and weight of the phased array radar are greatly reduced. The shape of the phased array radar can be changed, to make the phased array radar apply in various complex environments. The flexible substrate with the transient self-destroying characteristic makes an electronic device destroy under required condition, to guarantee safety of military secrets and keep technology advantages. The flexible phased array radar can be widely applied in the field of military.