This paper has analyzed the conventional glitch-free clock multiplexers. An improved glitch-free clock switching circuit is proposed, which introduces fault-tolerant function that is able to switch away from a failed clock, and adds configurable bit that controls the switching clock edge. It is quite suitable used as a global clock multiplexer in FPGA. This switching circuit achieves three basic functions: clock select, clock enable, and clock disable. As the configurable low-level triggered latch is proposed, switching time is reduced by 1/3 compared to the double D flip-flops type clock multiplexer. This proposed switching circuit operates at 100 MHz with 17uW power consumption using TSMC 0.13um CMOS process parameters with a supply voltage of 1.5V.

A novel Built-In-Self-Test (BIST) approach is present in this paper to test the clock manager DLL of system-on-chip (SoC). The whole approach is divided into two steps. Firstly, test a single DLL which will be used as the benchmark in step two by introducing a test clock which is the jitter embodiment of the reference clock. The proposed method with a view to test the reference clock jitter tolerance. In the second step, the purpose is testing all the DLLs of SoC by traditional BIST approach based on comparison. And use the output response analyzer (ORA) to judge the comparison result. The proposed approach is widely suitable for test DLL of SoC rapidly and simply without complex test equipments.

A novel configurable no dead-zone digital phase detector is proposed in this paper. As an embedded SRAM is employed to store configuration data, detection sensitivity of the phase detector can be controlled by the configuration data according to different input frequency. Besides, the novel phase detector avoid dead-zone by adopting two flip-flops and generating three state during operation. The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA). The PD is designed to betake in the frequency range of 25 MHz to 200 MHz. Simulation result for the proposed circuit realized with 0.18 um CMOS technology.

A novel configurable frequency synthesizer based on delay-locked-loop (DLL) is presented in this paper, with maximum multiplication factor 10 and maximum division factor 16. A SRAM is employed to store configuration data for different multiplication and division factor. Users only need to change the data stored in the embedded SRAM to obtain frequency needed. The output frequency range is from 25 MHz to 1 GHz using tsmc 0.18 mum CMOS process parameters. The locking time of the DLL core is 20 mus at 100 MHz and 120 mus at 25 MHz. The cycle-to-cycle jitter of the DLL is 60 ps.The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA).