This paper presents a low-power 112-Gb/s edge-replicated PAM-4 transmitter (TX) designed in a 28-nm CMOS process with a low reference clock bandwidth required and low-jitter clocking scheme. The proposed TX replicates the single 1-UI edge-detection pulse to act on both the pre- and post-taps with a single pre-driver slice, and performs modulation at the Current mode logic (CML) driver stage, which extends the bandwidth and saves area and power consumption. A ring voltage controlled oscillator (RVCO)-based injection-locked oscillator (ILO) with clock multipliers is employed to drive the quarter-rate TX architecture by 1/8-baud-rate reference clocks, which achieves low jitter and power consumption. Post-layout simulation results demonstrate that the TX can equalize a channel with over 7.74-dB insertion loss at the Nyquist frequency. Operating at 0.8-V supply, the TX consumes a total power of 79.07 mW, achieving an energy efficiency of 0.71 pJ/bit, and occupying an area of 0.259 mm2.

Error Vector Magnitude (EVM) is a pivotal metric for evaluating the modulation quality and comprehensive performance of digital receivers. As programmable Radio Frequency (RF) transceivers evolve toward System-on-Chip (SoC) architectures-where RF analog front-ends and digital basebands are deeply integrated-traditional testing methods relying on external Vector Signal Analyzers (VSA) face significant challenges, such as inaccessible digital interfaces and fragmented testing links. This paper proposes an FPGA-based on-chip EVM selftest method. By constructing a virtual VSA and Vector Signal Generator (VSG) within the system, a complete workflow for QAM modulation/demodulation and EVM calculation is established. Through the optimization of shaping filter parameters and improvements in timing and carrier synchronization algorithms, the proposed method achieves high-precision measurement while maintaining hardware resource efficiency. Experimental results demonstrate that this method offers excellent stability and engineering feasibility, providing a low-cost, deployable solution for the performance verification of highly integrated RFSoCs.

This paper presents a low-power 32 Gb/s NonReturn-to-Zero (NRZ) transmitter (TX) designed in a 28 nm CMOS process, optimized for high-loss channel environments. To address the excessive power consumption of conventional deemphasis Feed-Forward Equalizer (FFE) in long-reach applications, a novel Edge-Boosting FFE architecture is proposed. A modified Minimum Mean Square Error (MMSE) tap-coefficient adaptation algorithm is developed to ensure equivalent equalization performance with enhanced energy efficiency. Furthermore, a low-power clock distribution network is implemented using an Injection-Locked Oscillator (ILO) based clock generator. Post-layout simulation results demonstrate that the proposed transmitter effectively compensates for a steep channel loss of 80 dB at 16 GHz. Compared to a conventional 3-tap FIR-based TX, the Edge-Boosting pre-emphasis driver achieves an 11.2% reduction in power consumption. The complete TX occupies a layout area of 0.39 mm2 and achieves a power efficiency of 0.57 pJ/bit at 32 Gb/s (excluding LC-PLL power), offering a robust and energy-efficient solution for next-generation high-speed serial links.

This paper proposes an automatic sleep circuit for reducing the static power consumption of memory blocks in FPGAs. In contrast to the traditional design approach focused on SRAM cells, this paper designs an external control circuit based on the memory enable (EN) signal with configurable sleep latency, addressing the significant increase in static power consumption caused by the growing number of embedded memory blocks in FPGAs. The core concept of the circuit is as follows: when a memory block is not accessed for a user-defined number of delay cycles, the circuit automatically generates a sleep signal to turn off the internal switches and the external input clock of the memory, entering a low-power state. Once the memory is accessed again, the circuit can wake it up rapidly within 2 cycles. The circuit uses thermometer code decoding for the delay parameter and employs a cascaded latch structure with dedicated sleep signal generation logic to achieve precise delay control and reliable sleep/wake-up timing. In sleep mode, power savings exceed 80% compared to both standby mode and active mode. The proposed scheme provides a flexible power management strategy for FPGA memories, allowing optimization based on different application access patterns, effectively reducing system power consumption while ensuring performance.

With the development of FPGA circuit, the memory density improvement has become the pivot. The True Dual-Port SRAM has the disadvantage in memory density because of 8 T SRAM bitcell. Therefore, some design of FPGA circuits try to replace the True Dual-Port SRAM by Pseudo Dual-Port (PDP) SRAM SRAM partially. However, how to realize the similar function for PDP SRAM is a problem. This paper proposed a novel design for the function convert for 2-Read-Write (2RW) PDP SRAM, and the designed circuit can also be used for improving the performance of Double Pumping Clock (DPC) circuit and address input circuit. The designed SRAM is based on FinFET technology, and the read access time of port-A and port-B are 362 ps and 741 ps respectively with 0.8 V operating voltage. The measure result shows that the memory density achieves $\mathbf{6. 5 2 ~ M b} / \mathbf{m m 2}$.

This paper presents a lightweight method for analyzing sensitive points of the Hardware Design Language (HDL)-designed circuit implemented in aerospace-grade Static RAM (SRAM)-based Field-Programmable Gate Arrays (FPGAs), which are prone to Single-Event Upsets (SEUs) due to radiation in space environments. The proposed method leverages circuit netlists and layout information to model the FPGA circuit as a directed graph, where instances are nodes and nets are edges. Two algorithms are introduced: one identifies the longest forward propagation paths, and the other determines nodes with the maximum downstream connectivity. These algorithms efficiently pinpoint critical nodes that are more likely to cause circuit errors when affected by SEUs. The method is validated through fault injection experiments on Xilinx VU3P FPGAs, demonstrating that the identified sensitive nodes have a significantly higher fault frequency compared to randomly selected nodes. The results confirm the accuracy and effectiveness of the proposed approach, offering a rapid and reliable way to detect and mitigate soft errors in aerospace applications. This advancement is crucial for enhancing the reliability of FPGA-based systems in radiation-prone environments.

Loopback delay is a critical metric for evaluating the real-time performance of programmable RF transceivers in wireless communication, radar, and measurement systems. Conventional measurement approaches often rely on external signal generators and oscilloscopes, resulting in complex setups and susceptibility to instrument-induced errors. This paper presents a fully FPGA-based loopback delay testing method utilizing internal zero-crossing signal generation and detection. The proposed approach was implemented and validated on the Hongxin chip developed by the Beijing Microelectronics Technology Institute. The method requires no external instruments or additional configuration, offering fast, stable, and accurate measurement results. It is versatile and can be widely applied to FPGA+RF transceiver architectures in various system platforms.

Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space applications are highly susceptible to single event effects, leading to soft errors in FPGAs. Additionally, as FPGAs scale up, the difficulty of correcting soft errors also increases. This paper proposes that performing soft error sensitivity analysis on FPGAs can help target the more sensitive areas for detection and correction, thereby improving the efficiency of soft error repair. Firstly, in accordance with the dual-layer architecture of SRAM-based FPGAs, methods for the soft error sensitivity analysis of FPGA application layer resources and configuration bitstreams are reviewed. Subsequently, based on the analysis results, it also covers corresponding application layer memory scrubbing and configuration scrubbing techniques. A prospective look at emerging soft error mitigation technologies is discussed at the end of this review, supporting the development of highly reliable aerospace-grade SRAM-based FPGAs.

SoPC has gradually take place of FPGA in electronic systems. Protecting the bitstream files designed by users becomes the basis of using digital chips safely. In this paper, a security configuration circuit in SoPC chip is proposed. Through the encryption and authentication algorithms of AES-256 and SHA-256, and the unique readback control circuit, we realized the encryption configuration and bitstream authentication of the SoPC chip. Meanwhile, effectively protects against possible backdoors and loopholes in SoPC. The simulation results show that the circuit can realize encryption configuration and data protection.

With the progress of Integrated Circuit technology and the multiple needs of human for scalar and reconfigurable operations in intelligent electronic system, a new chip architecture combining traditional FPGA and embedded processor appears, namely programmable SoC. Programmable SoC products have been widely used in mission and safety-critical applications, but production defects in hardware and time-related defects in the working process often lead to system misbehavior, which leads to disastrous consequences. Therefore, in view of the long-term reliability application requirements of programmable SoC products, it is necessary to carry out relevant research on its in-field test technology. In this paper, we will use the Software-Based Self Test (SBST) method to explore and implement the function of data cache controller for Zynq-7000 series Programmable SoC embedded processors (Enable\Disable, Invalidate, Clean) test technology research. By making full use of the fully programmable features of hardware and software resources in Zynq-7000, we have respectively realized the test generation technology based on PS and the test observation technology based on PL, and designed the prototype test system. Finally, the experimental results show that the prototype test system meets our expectations and can realize the in-field test of the cache controller of the embedded processor in the Zynq-7000 series programmable SoC. At the end of this paper, we summarize the work done and look forward to the future research direction.

SoPC has gradually take place of FPGA in electronic systems. Configuration is basics and manifestation of the flexibility and customization when using SoPC chip. In this paper, a multi-mode configuration circuit embedded in SoPc chip is proposed. Relying on electrical level of external pins set by user, the circuit can switch among different modes and reading configuration bitstream data from different storage medium. CPU-dominated configuration, traditional FPGA configuration and JTAG configuration all consider about the usability and convenience and configuration speed of SoPC chip. The simulation results show that this circuit can configure SoPC chip in various modes according to user's requirements.

With the advancement of integrated circuit technology and the pressing need for Hardware-Software Codesign in real-world scenarios, FPGA producers started to set in processor cores in the chip design, resulting in the emergence of a new circuit architecture with both software and hardware programmable features, dubbed programmable SoC. In comparison to standard FPGA, the architecture and functioning characteristics of programmable SoC have evolved dramatically. As a result, in the mass production testing, the same bitstream configuration approach based on the SelectMAP interface as regular FPGA is unable to achieve. This study presents a mass production test bitstream configuration method based on a reconfiguration mechanism for the Xilinx Zynq-7000 series programmable SoC. This technology is mainly made up of three sections: program solidification and test bitstream storage based on SD card, bitstream reconfiguration based on PCAP path, and configuration bitstream switching based on GPIO interrupt. Finally, the proposed technology is verified by experiments, and experiments are designed to compare the test configuration time based on JTAG path and PCAP path. In contrast, this technology has the characteristics of high configuration efficiency and can be fully applied to the mass production test of this series of Programmable SoC circuits.

In order to meet the increasing clock requirements of FPGAs, Phase-locked loop has been widely used in FPGAs as clock management unit. This paper introduces a charge pump phase-locked loop with dual voltage-controlled oscillator applied on a 28nm FPGA platform. On the basis of the traditional charge pump phase-locked loop, this paper designs a configurable filter, a new structure of VCO with amplification and shaping circuit. The simulation results show that the structure can effectively improve the frequency locking speed of the VCO.

This paper introduces a programmable I/O buffer that supports multiple differential standards. It is integrated in a 28nm process FPGA to implement the communication between the FPGA core and external circuits. Under different standards, its data transmission rate can reach 1.25Gbps. In the article, the design idea of important circuit modules that work with I/O buffer, such as single-ended to differential-ended module, and bias signal generation module are also introduced. On the other hand, because all circuit designs use 1.8V devices and the supply voltage of the supported differential standard is higher than 1.8V, it also has a voltage withstand function under 2.5V power supply. After the circuit design is completed, the layout is drawn. According to the simulation results, its function is correct and the transmission rate can reach the design value.

This paper introduces a dual power bus transceiver structure with multi-voltage to solve the data exchange problem between low-voltage FPGA core devices and high-voltage peripheral control circuits. Its design idea is based on the multi-voltage I/O buffer, and some important control circuits are used to change its working state to ensure that the circuit works normally under different level standards. The difficulty of the design is how to use 3.3V devices to make the input/output reach 5V which is higher than the device voltage, so it is necessary to design a suitable withstand voltage control module. Finally, design of the transceiver was implemented in a fully customized chip. After experimental testing, it is found that its function is correct, and the transmission speed, main delay parameters, and driving ability have good results.

With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

In this paper, a field programmable gate array (FPGA) I/O cell developed to support 1.25 gigabits-per-second source-synchronous standard is presented. The I/O cell provides the compatibility of 38 high-speed I/O standards, features wide supply voltage range, 3.3V voltage tolerance. To achieve the speed and performance, a build-in serializer de-serializer (SERDES) and a DLL-compensated delay chain are introduced into the I/O cell. The proposed I/O cell has been fabricated and integrated in an SRAM-based FPGA with commercial 65nm CMOS process.

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts’ running or halting the FPGA device.

In this paper, a field programmable gate array (FPGA) I/O buffer developed to support 1.25 gigabits-per-second differential source-synchronous standards is presented. The I/O buffer provides the compatibility of 38 high-speed I/O standards, features wide supply voltage range, programmable drive strength and controlled impedance driver. To enhance the performance and drive capacity of low voltage standards, an auxiliary supply is introduced into the I/O buffer. The proposed I/O buffer has been fabricated and integrated in an SRAM-based FPGA with commercial 65nm CMOS technology.

Partial reconfiguration is a technology that the different bitstream is loaded into reconfigurable region to realize the different functions. Partial reconfiguration be able to make reconfigurable time shorten greatly and implement time division multiplex access of logic resources. JTAG (Joint Test Action Group) is an essential module of FPGA (Field Programmable Gate Array), accomplishing testing, configuration and soon. As the result of supporting user-defined instruction, JTAG circuit has the good extensibility. In order to implement partial reconfiguration of logic resources, this paper puts forward dynamic reconfiguration instruction-DRP, and designs the JTAG circuit of accomplishing dynamic reconfiguration.