The complexity of resistive random-access memory (RRAM) based neuromorphic computing systems (RNCS) and the variety of faults make on-line testing challenging. We propose an Iterative Fast Gradient Sign Method (IFGSM) for enhancing the fault sensitivity of RNCS tests. This is accomplished by exploiting the sensitivity of neural networks to weight perturbations. This method is able to enhance the sensitivity to fault perturbations using tests applied only to the primary I/O. Statistical analysis shows that the tests based on IFGSM are more sensitive to small changes in the RNCS than standard test approach.

Memristive backpropagation (BP) neural network in-situ training is of significant importance for accelerating data processing. Currently, three main challenges hinder circuit design of the in-situ training memristive BP neural network: first, achieving circuit timing control without computer assistance is difficult; second, for the existing memristive BP neural network, it is hard to convert the change of weight values to memristance change; third, there is a lack of memristor control strategy suitable for in-situ training. To address the three challenges, this paper proposes a timing control method that does not require computer assistance, utilizing MOS transistors and analog value storage circuits to divide the training of the memristive BP neural network into four phases. Next, a novel memristor array is designed in which memristance correspond to the weight value linearly. Therefore, the weight change obtained by BP algorithm is convenient to be transferred as memristance change. Then, characteristics of the memristor are analyzed to map the memristance change as the corresponding control pulse. The amplitude of the control pulse are calculated by the multiplication and division circuit. Finally, XOR, iris classification, and MNIST digit classification experiments are conducted on the proposed memristive BP neural network circuit, proving that the proposed circuit design has good performance.

The bidirectional long short-term memory (BiLSTM) network involves significant amount of parameter computations. This paper proposes the memristor-based bidirectional long short-term memory (MBiLSTM) network, with its capability of in-memory computing and parallel computing, can accelerates the parameter computations speed. The MBiLSTM network circuit is composed of normalization circuit, two memristor-based long short-term memory (LSTM) circuits, memristor-based resnet circuit, memristor-based dense circuitand winner-take-all (WTA) circuit. The voltage signals are scaled to the setting range by normalization circuit, memristor-based LSTM circuit is responsible for extracting features from the dataset, memristor-based resnet circuit can enhance the overall performance of the network, memristor-based dense circuit ensures that the final outputs dimension matches the dimension of the target signals, WTA circuit outputs the maximum voltage of memristor-based dense circuit. The effectiveness of the MBiLSTM network is validated through gait recognition experiment and handwritten digit recognition experiment. The stability, robustness and potential errors in the manufacturing process of memristance are analyzed.

Currently, studies on memristor-based operant conditioning circuits concentrate on the learning process of the single behaviors, without attention to the chaining process composed of multiple behaviors. This paper proposes a memristor-based circuit design of biological behavior chain, which consists of behavior modules, learning modules, delay modules, and satiety modules. After learning, the mouse can complete a chain process consisting of three behaviors: pressing button A to eliminate electrical stimulation, pressing button B to obtain food, and pressing button C to open the cage. Behavior and delay modules are used to simulate these three behaviors, the learning module is used to simulate the learning process of chaining between two behaviors and chaining between three behaviors. In addition, the study also explored the effects of mouse satiety on the experiment, as well as processes such as natural forgetting and relearning. The simulation results in PSPICE indicate that the circuit is capable of effectively simulating the aforementioned functions. Furthermore, Monte Carlo analysis and temperature simulation analysis are conducted on the circuit. The simulation results confirm that the circuit exhibits good stability.

Memristors, as a novel non-volatile circuit component, hold significant promise in electronic circuit applications. This article presents a novel memristor-based multiplier design, consisting of three key stages: an absolute value circuit, a multiplication circuit, and a sign circuit. The multiplier is capable of performing multiplication operations within the range of 1V to 10V, and it can achieve multiplication even when both input values are set to zero through deliberate circuit design, thereby eliminating the need for analog-to-digital signal conversion. This innovation reduces circuit complexity and energy consumption, enhancing overall circuit efficiency.

Multipliers are extensively utilized in circuit design across various applications. Generally, there are two types of multiplication circuits available. The first type is the digital multiplier used in digital circuits, which requires the addition of power-consuming A/D (D/A) converters. The second type is the analog multiplier represented by the Gilbert multiplier, which operates solely in high-frequency circuits and has specific requirements for input and output signals. Multiplication plays a vital role in the hardware implementation of artificial intelligence algorithm training. However, the current multiplication circuits are not suitable for this specific circuit design scenario. To address the limitations of current multiplication circuits, this paper proposes a novel analog multiplier. The proposed multiplier in this paper consists of three main components: the absolute value circuit, the multiplication operation circuit, and the sign operation circuit. Firstly, the input voltage is passed through the absolute value circuit to obtain its absolute value. Then, the unsigned multiplication operation is performed using the multiplication operation circuit. Finally, the sign operation circuit adds the appropriate sign to the unsigned result and completes the output. The circuit is simulated and analyzed using PSPICE. It achieves an input voltage range of -10V to +10V and an output range reaches tens of volts. In comparison to traditional circuits, the proposed analog multiplier presented in this paper offers a significantly wider input and output range. Furthermore, its precision can be adjusted by adding circuit components. This paper introduces a novel technical approach for the design of a fully hardware-implemented multiplication circuit in artificial intelligence algorithm training.

Due to the limitations of computation capability and memory of GPUs, most image restoration tasks are trained with cropped patches instead of full-size images. Existing extensive experiments show that the model trained with a larger patch size could achieve better performance since a larger patch size typically means larger receptive fields. However, it comes at the cost of extremely long training times and significant memory consumption. To alleviate the dilemma mentioned above, we propose a multi-patch method to expand the receptive field with negligible memory and computation increase (less than $$1\%$$ ). In addition, we collect 100K high-quality images of 1K categories, following ImageNet, from flickr.com for low-level image tasks. Our method improves the quantitative performance by 0.3412dB on the validation set of the "Compressed Input Super-Resolution Challenge - Image Track".

The traditional mirror current source circuit has been widely used in analog circuits. However, the output current of this circuit is not adjustable after the circuit is manufactured, which is a difficult issues. To solve this problem, this paper proposes a memristive continuously adjustable cascode current source. In this paper, we introduce two additional MOS transistors and a memristor to the circuit architecture of the cascode current mirror. This modified design achieves electrical isolation between the improved cascode current source and the memristor control circuit. By incorporating a memristor control circuit, we are able to regulate the memristance in the main circuit, which in turn allows for continuously adjustable output current. The mathematical relationship between the control signal and the output current of the memristor control circuit is derived in this paper, and the mathematical model is verified using PSPICE. The simulation results show that the continuously adjustable cascode current source based on the memristor achieves continuous regulation of the output current and high accuracy of the output current. This paper provides a technical solution to the problem that the traditional current source circuit cannot realize the continuous adjustable output current.

The strain technology is accelerating the progress on the CMOS compatible Ge-on-Si laser source. Here, we report a monolithically integrated microbridge-based emitting-detecting configuration, equipped with lateral p–i–n junctions, waveguide and gratings. The operating wavelength range of the emitting bridge and the detecting bridge are matched through the designed same dimensions of the two microbridges, as well as the strain. Strain-enhanced spontaneous emission and the effect of spectra red-shifting on low-loss transmission of on-chip light are discussed. Temperature dependence experiments reveal that in devices with highly strain-enhanced structure, the strain variation can offset the effect of electron thermalization, so that the performance of the device remains stable when temperature changes around room temperature.

We propose and design aluminum nitride slot waveguides with acoustic pumping to achieve large forward stimulated Brillouin scattering. The slot structure can constructively add to or destructively interfere with optical forces. The novel arrangement of symmetric electrodes can provide out-of-plane electric fields for piezoelectric materials and excite acoustic waves that satisfying the necessary phase-matching. In this work, the pump photons is intramode scattered into an anti-Stokes sideband by injected phonons. Our aluminum nitride slot waveguide is partly suspended on the silica glass to avoid the leakage of acoustic wave. The height of this waveguide is set to 500 μm and the gap is set to 50 μm. The distance between the electrode and the waveguide is flexible to adjust the piezomechanical coupling strength. Our proposed scheme offers an effective approach to implement acousto-optic interaction in integrated silicon photonics.

Abstract We design and demonstrate an asymmetric Ge/SiGe coupled quantum well (CQW) waveguide modulator for both intensity and phase modulation with a low bias voltage in silicon photonic integration. The asymmetric CQWs consisting of two quantum wells with different widths are employed as the active region to enhance the electro-optical characteristics of the device by controlling the coupling of the wave functions. The fabricated device can realize 5 dB extinction ratio at 1446 nm and 1.4 × 10−3 electrorefractive index variation at 1530 nm with the associated modulation efficiency VπLπ of 0.055 V cm under 1 V reverse bias. The 3 dB bandwidth for high frequency response is 27 GHz under 1 V bias and the energy consumption per bit is less than 100 fJ/bit. The proposed device offers a pathway towards a low voltage, low energy consumption, high speed and compact modulator for silicon photonic integrated devices, as well as opens possibilities for achieving advanced modulation format in a more compact and simple frame.

We report holographic fabrication of nanoporous distributed Bragg reflector (DBR) films with periodic nanoscale porosity via a single-prism conuration. The nanoporous DBR films result from the phase separation in a material recipe, which consists of a polymerizable acrylate monomer and nonreactive volatile solvent. By changing the interfering angle of two laser beams, we achieve the nanoporous DBR films with highly reflective red, green, and blue colors. The reflection band of the nanoporous DBR films can be tuned by further filling different liquids into the pores inside the films, resulting in the color change accordingly. Experimental results show that such kinds of nanoporous DBR films could be potentially useful for many applications, such as color filters and refractive index sensors.

The full exploration of Si-based photonic integrated circuits is limited by the lack of an efficient light source that is compatible with the complementary metal–oxide–semiconductor process. Highly strained germanium (Ge) is a promising solution, as its band structure can be fundamentally altered by introducing tensile strain. However, the main challenge lies in the incorporation of an electrical structure while maintaining high strain with uniform distribution in the active region. Here we present highly strained Ge LEDs driven by lateral p–i–n junctions and report the strain-induced enhancement of electroluminescence (EL) from Ge. Raman characterization shows that 1.76% strain along the ⟨100⟩ direction with relatively uniform strain distribution is achieved. The observed strain-induced red-shifts of EL spectra agree well with the theoretical prediction, revealing that the direct band gap of Ge can be tuned in the range of 0.785 eV (1580 nm) to 0.658 eV (1885 nm). This work offers a pathway toward a stra...

The rising penetration of intermittent renewable distributed generation leads to uncertainties in the planning of electric distribution networks. Fully considering the uncertainties pertinent to wind power generation, photovoltaic power generation and load demand, this paper proposes a scenario-based model for the planning of active distribution systems. The solution obtains the optimal capacities and locations of wind and photovoltaic based distributed generators in the distribution system, whilst minimizing the active and reactive power losses as well as voltage deviation. A scenario matrix is generated using the heuristic moment matching technique that captures the stochastic moments and correlation among historical wind and photovoltaic power, and electricity demand. The scenario matrix is then incorporated to propose a stochastic planning model that considers a multi-objective index for minimizing power losses and voltage deviation. Finally, the effectiveness of the proposed planning model is confirmed using case-studies in 53-bus and IEEE 123-bus distribution systems.

The polymer/liquid-crystal composite materials have been extensively studied for their potential applications. Various optical devices based on this composite material have been proposed and realised. The device performance is highly dependent on the phase separation of this composite material. Here, we investigate the photopolymerisation-induced phase separation in this composite material. Depending on the mass ratios between the polymer and the liquid crystal, the phase separation can be well controlled and subsequently affect the morphological and electro-optical properties. At a fixed ratio, we can realise either phase-separated composite films or conventional polymer-dispersed liquid crystal films with completely different optical properties. By carefully controlling the exposure conditions, the morphologies and electro-optical properties have been studied and optimised in details. With in-depth studies and optimisation, the photopolymerisation-induced phase separation technique could be utilised to realise many different optical functions based on the polymer/liquid-crystal composite materials.

Emerging memristor devices like metal oxide resistive switching random access memory (RRAM) and memristor crossbar have shown great potential in computing matrix-vector multiplication. However, due to the nonlinear distribution of resistance levels in memristor devices, the state-of-the-art multi-bit cell cannot accomplish the multi-bit computing task accurately. In this paper, we propose fault-tolerant schemes to rescue memristor-based computation with nonlinear resistance levels. We classify the resistance level distributions in memristor devices into three types, and the corresponding models are proposed to analyze the computation characteristics. We propose two theoretical conditions to determine if a memristor device can support multi-bit matrix computation. For the deviated linear model, the least squares method is used to reduce the computing error. When the resistance distribution obeys the proposed power model, a logarithmic operation circuit is used to decode the multiplication results and then accomplish the computing accurately. For the exponential model, since the device cannot complete typical matrix-vector multiplication from hardware level, we propose online and offline quantization methods to make the neural computing algorithms friendly to memristor device. Simulation results show that the root-mean-square error improves around 4% with the linear model and more than 99% with the power model. After quantization, the accuracy of ResNet-18 using memristor with exponential conductance levels can be improved to the same accuracy with ideal linear devices.

Convolutional Neural Networks (CNNs) have achieved excellent performance on various artificial intelligence (AI) applications, while a higher demand on energy efficiency is required for future AI. Resistive Random-Access Memory (RRAM)-based computing system provides a promising solution to energy-efficient neural network training. However, it's difficult to support high-precision CNN in RRAM-based hardware systems. Firstly, multi-bit digital-analog interfaces will take up most energy overhead of the whole system. Secondly, it's difficult to write the RRAM to expected resistance states accurately; only low-precision numbers can be represented. To enable CNN training based on RRAM, we propose a low-bitwidth CNN training method, using low-bitwidth convolution outputs (CO), activations (A), weights (W) and gradients (G) to train CNN models based on RRAM. Furthermore, we design a system to implement the training algorithms. We explore the accuracy under different bitwidth combinations of (A,CO,W,G), and propose a practical tradeoff between accuracy and energy overhead. Our experiments demonstrate that the proposed system perform well on low-bitwidth CNN training tasks. For example, training LeNet-5 with 4-bit convolution outputs, 4-bit weights, 4-bit activations and 4-bit gradients on MNIST can still achieve 97.67% accuracy. Moreover, the proposed system can achieve 23.0X higher energy efficiency than GPU when processing the training task of LeNet-5, and 4.4X higher energy efficiency when processing the training task of ResNet-20.

Convolutional Neural Networks (CNNs) play a vital role in machine learning. CNNs are typically both computing and memory intensive. Emerging resistive random-access memories (RRAMs) and RRAM crossbars have demonstrated great potentials in boosting the performance and energy efficiency of CNNs. Compared with small crossbars, large crossbars show better energy efficiency with less interface overhead. However, conventional workload mapping methods for small crossbars cannot make full use of the computation ability of large crossbars. In this paper, we propose an Overlapped Mapping Method (OMM) and MIxed Size Crossbar based RRAM CNN Accelerator (MISCA) to solve this problem. MISCA with OMM can reduce the energy consumption caused by the interface circuits, and improve the parallelism of computation by leveraging the idle RRAM cells in crossbars. The simulation results show that MISCA with OMM can achieve 2.7× speedup, 30% utilization rate improvement, and 1.2× energy efficiency improvement on average compared with fixed size crossbars based accelerator using the conventional mapping method. In comparison with GPU platform, MISCA with OMM can perform 490.4× higher on average in energy efficiency and 20× higher on average in speedup. Compared with PRIME, an existing RRAM based accelerator, MISCA has 26.4× speedup and 1.65× energy efficiency improvement.

The emerging metal-oxide resistive switching random-access memory (RRAM) devices and RRAM crossbar arrays have demonstrated their potential in enormously boosting the speed and energy-efficiency of analog matrix-vector multiplication. Unfortunately, due to the immature fabrication technology, commonly occurring Stuck-At-Faults (SAFs) seriously degrade the computational accuracy of RRAM crossbar based Computing System (RCS). In this paper, we propose a Mapping Algorithm with inner fault-tolerant ability (MAO) to convert matrix parameters into RRAM conductances in RCS by providing larger mapping space and fully exploring the available mapping space. Furthermore, we present two computation-oriented redundancy schemes — ‘Redundant Crossbars’ (RX) and ‘Independent Redundant Columns’ (IRC) to alleviate the loss of computational accuracy due to SAFs. RX adds redundant RRAM crossbar arrays and IRC introduces independent redundant RRAM columns to compensate the computational errors brought by SAFs.