Doping, which has been extensively studied in the past century, is essential for tuning the electrical conductivity of semiconductors. However, the effect of doping on the thermal conductivity of semiconductors has been much less studied despite the growing importance of electronics cooling. A clear understanding of defect-phonon scatterings remains elusive due to difficulties in well-controlled growth of crystals and advanced thermal and structural characterizations. Herein, by combining advanced characterizations and high-quality growth of cubic silicon carbide (3C-SiC) single crystals with well-controlled boron doping, we experimentally observe an extremely strong defect-phonon scattering intensity. This effect exceeds the prediction of the classic mass-difference model by tens of times in magnitude. At the doping level of 1019 cm-3, a 50% reduction of thermal conductivity was achieved-the highest reductions reported for common semiconductors. The measured thermal conductivity of B-doped 3C-SiC matches first-principles predictions with excellent agreement, demonstrating the critical role of low-frequency phonon resonant scattering. The influence of strain gradients on thermal transport was excluded by local vibrational spectra scanning through atomic-resolution phonon-level electron energy loss spectroscopy. Our findings not only shed light on the fundamental understanding of defect-phonon interactions but will also impact applications such as thermal management of electronics.

As a critical enabler for advanced technology, direct backside contact (DBC) demands careful source/drain (S/D) engineering to unlock its full performance benefits. In this study, S/D epitaxial expansion yields approximately 100 percent bottom channel strain enhancement and over 40 percent Ion increase without short channel effect degradation. Moreover, increasing the S/D bulk doping reduces Ron by 20 percent, thereby enhancing ring-oscillator (RO) performance. The DBC-driven DTCO would pave the way for sub-1nm technology node.

Strain engineering is essential for boosting the performance of gate-all-around field-effect transistors (GAAFETs). However, the visualization of strain distribution at the atomistic scale is challenging. This study systematically investigates the width-dependent strain distribution in Si/SiGe stacked nanosheets by using high-resolution scanning transmission electron microscopy (STEM) images. Dynamic and quantitative strain mapping results show that the compressive strain in Si layers increases with nanosheet width, indicating suppressed relaxation in wider structures. These findings clarify the geometric-size-dependent strain modulation mechanism and provide guidance for optimizing stress engineering and enhancing carrier transport in next-generation GAA devices.

Artificial Intelligence (AI), has been occupying the central position in recent technological advancement, propelled by exponentially increasing computing resources, which in turn stimulate the demand on higher level 3D integration for integrated circuits. However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the "Flip 3D" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce "Hyper 3D" (H3D) technology for dual-sided system-on-wafer integration. Our results validate that this unified dual-sided scheme provides effective solution to the "computing," "memory," and "connectivity" walls. This work establishes a scalable roadmap for multi-layer on-chip systems, providing a full-3D hardware strategy for the next generation of AI hardware.

With the development of three-dimensional integrated circuits (3D ICs), thermal management has become a critical challenge due to the poor thermal conductivity (TC) of nanoscale interconnects. This study investigates the thermal transport properties of interconnect layers in 16 nm and 5 nm technology nodes using time-domain thermoreflectance (TDTR) and finite element modeling (FEM). The results demonstrate that the effective TC of the interconnect stack is predominantly constrained by thermal boundary conductance (TBC) rather than the intrinsic properties of the constituent materials. The active layer also exhibits a low thermal conductivity even below 1 W•m⁻¹•K⁻¹, creating a major bottleneck for heat dissipation in 3D ICs.

Complementary FET (CFET) architectures are promising for logic scaling, especially when combined with backside power delivery networks (BSPDNs). In this work, we propose a CFET architecture featuring an embedded interconnect (EI) layer (EI-CFET), enabled by sequential process integration. By redistributing signal and power routing across the frontside (FS), EI layer, and backside (BS), the proposed architecture enables a 3T standard-cell height (CH) and reduces the cell area by approximately 25% and 20% relative to the 4T and 3.75T FS-/BS-routed reference CFET cells, respectively. The EI layer alleviates routing-induced parasitic penalties by shortening critical connections and improving routing flexibility, leading to more pronounced performance benefits in cells with denser internal routing. Meanwhile, connection failures induced by top-to-bottom misalignment can be effectively mitigated by an optimized EI handoff structure, and the performance variation is suppressed to below 0.5%. In addition, independent crystallographic optimization of stacked devices provides additional performance gains exceeding 6% over the reference design. These results demonstrate that the EI-CFET is a promising candidate for high-density and high-performance 3-D CMOS technologies.

Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scaling. For the first time, this work systematically investigates the state-of-the-art Drain Merge through Active (DMtA), a revolutionary technology reported recently with the DM embedded in the active region, through a comprehensive DTCO framework spanning process integration, contact-configuration-dependent (CTCD) compact modeling, standardcell design, RO evaluation and block-level PPA benchmark on a 32-bit RISC-V Ibex core. By reducing DM parasitics and enabling DM-width optimization, DMtA improves RO frequency by 11.7

Switching asymmetry in hafnium oxide (HfO2)-based ferroelectric capacitors severely degrades retention and endurance, limiting their application in nonvolatile memories. In this work, the pronounced initial switching asymmetry manifested as a bias field (Ebias) of 0.22 MV/cm in Ga-doped HfO2 (HGO) capacitors is suppressed by introducing an ultrathin NbOx interfacial layer. The optimized device achieves a highly symmetric polarization loop (Ebias ~ 0), a large remanent polarization (2Pr = 35 μC/cm2), a low coercive field (Ec = 0.78 MV/cm), excellent endurance, and robust retention. This enhancement is attributed to a directional compensation field (Ecomp) established by the NbOx layer. This field neutralizes the intrinsic built-in field (Eint) arising from oxygen vacancies accumulated at the bottom interface, thereby restoring switching symmetry. This work provides a feasible interface-engineering pathway toward highly reliable HfO2-based nonvolatile memories.

In this work, CFET, as the key device candidate in sub-nm nodes, was carefully studied in terms of manufacturability. Considering the inevitable high aspect ratio (HAR) processes and wafer backside (BS) patterning, the structural variation of CFET was thoroughly examined by the process emulation. The sidewall slope variation of dummy gate and BS wafer thinning variation are identified as the most critical sources of device failure, which manifests as gate-to-S/D short. The CFET with conventional flow features a process window of 0-1.3° for the sidewall slope variation of dummy gate and shows high sensitivity to the substrate polishing residue (Sub. Residue), indicating process flow optimization needed (such as Flip FET). As for electrical impacts, RC parasitic variability from process variation was also analyzed, with quantitative assessment of the process robustness. Monte Carlo random experiments incorporating parasitic variability were further performed to validate the process challenges encountered in the device fabrication.

In this work, prospective review on sequential 3D integration (S3D) is carried in terms of low-temperature fabrications and high-density designs. Silicide-initiated lateral epitaxial crystallization (SILEC) is proposed to form high-quality single-crystal-like channel material at 550oC, featuring enhanced mobility. Ultra-thin self-limited TiSix (SL-TiSix) silicide is formed on the a-Si sacrificial layer and approaches ultra-low specific contact resistivity down to 1.63/4.23 nΩ-cm2 on Si:P and SiGe:B substrate at 350oC. With interlayer connect, S3D SRAM cell can contiunue the scaling-down trend from monolithic CFET SRAM.

Conventional polarization characterization techniques provide only the averaged response of ferroelectric films, limiting the investigation of domain-dependent reliability mechanisms in HfO2-based ferroelectrics. In this work, a new domain decoupling method is proposed to separately analyze ferroelectric domains with distinct switching behaviors. A three-domain model consisting of upward non-switchable domains, downward non-switchable domains, and switchable domains (Pd) is first introduced to describe heterogeneous domain populations during electrical cycling. By combining complementary switching-current measurements, the responses of different domain populations can be selectively extracted and reconstructed. The proposed method enables quantitative tracking of individual domain populations during cycling. As a demonstration, the method is further applied to analyze the time-dependent evolution of domain populations after electrical cycling. This approach provides a new route for investigating imprint, fatigue, and other reliability-related phenomena in ferroelectric devices.

With advanced logic transistor evolving rapidly and getting more complex, precise device’s resistance and capacitance partition is of growing significance in cutting-edge logic technology development, especially for the performance ramping. Unfortunately, the conventional wafer frontside test method faces intrinsic limitations in separating each resistance or capacitance component accurately. In this work, we proposed for the first time a dual-sided test method that fully exploits backside contact (BSC) to precisely partition the resistances of contact, S/D epitaxy and each channel as well as the gate-to-S/D metal capacitance ( ${C}_{\text {gmd}}\text {)}$ for future gate all around (GAA) nanosheet field-effect transistor (NSFET) with BSC. A well-calibrated technology computer-aided design (TCAD) deck was built to conduct a series of TCAD experiments and benchmark the method. TCAD-vs-test comparisons confirm an error below 10%, proving the method’s great accuracy, reliability, and robustness across a broader range of device geometries and features. In addition, the proposed capacitance partition method was further verified through TCAD, providing a unique way to understand device parasitic. This work provides a novel, effective, and extendable test method for resistance and capacitance partition, delivering powerful guidance for the future advanced logic technology node development.

In this work, to further enhance the routability and power–performance-area (PPA) of dual-sided vertical FETs (DSVFETs) for energy-efficient computing (EEC), we proposed and validated a novel End-Gated design that relocates the gate via from the vertical nanosheet side to its end. This placement clearly reduces parasitics and improves routability of the DSVFET. At the standard-cell level, the End-Gated design can shrink the area by 4% relative to the baseline with the Side-Gated design. On circuit level, by simulating a 15-stages INVD1 ring oscillator (RO), the End-Gated design shows 23% higher frequency at iso-power thanks to its lower parasitic capacitance, which is further consistently observed in other circuits with different vertical nanosheet numbers. As for the routability benchmark, more complex cell (XORD1) was studied, showing a 27.2% frequency gain in the End-Gated design benefited from less routing resource needed. Finally, the design was also evaluated with the dual-sided global signal (DGS). Placing pins on both sides of the wafer provides a 16.4% frequency benefit. These results position the End-Gated DSVFET as a practical path to further advance the VFET technology.

In this work, a thorough design technology co-optimization (DTCO) study was conducted on stacked transistors for A10 and A7 nodes, focusing on their unique design challenges from dual-sided power rails (PRs) and high-aspect-ratio interlayer vias (super vias). The overlapped PR configuration is more applicable to the stacked transistor layout design than the staggered PR one with at least 3.41% higher frequency at iso-leakage,thanks to its relaxed limits on nanosheet (NS) width (W-NS). Simultaneously, the placement of super vias including drain merge (DM) and gate merge (GM) was carefully studied for its impact on the parasitic RC and design space of W-NS, thereby affecting the circuit-level performance. For A10 node with the 3.5T cell design, optimal performance can be realized when the DM and GM are placed on opposite sides of the active region for less overlap capacitance, offering a further 9.0% frequency gain through fine tuning the DM width (W-DM), GM width (W-GM), W-NS, and NS number (N-NS). However, for 2.5T design, it performs the best when the DM and GM are placed on the same side for the lager W-NS in this configuration. Similarly, at A7 node with even more constrained W-NS, same-sided DM and GM placement performs the best for both 3.5T and 2.5T cells. Finally, the novel stepped-channel structure was introduced, with the conflict between W-NS and GM process solved and bringing 1.2% frequency benefit.

A low-temperature silicide initiated lateral epitaxial crystallization (SILEC) technique for 3D transistor stacking is experimentally presented in this work. With barrier modulated phase (BPM) controlled ultrathin NiSi2 as seeds, large size single-crystal-like Si grains up to 4.03 are formed under 600 oC. It’s exploited that the orientation consistency and boundary control can be achieved by film thickness constraints asymmetrical seed window design, respectively. As a result, uniform device characteristics are obtained, featuring low sub-threshold swing (~150 mV/dec) and high hole mobility (~40 cm2/V-s).

In this article, we present a contact resistivity extraction method calibrated using a de-embedding structure, called High-Resolution Transmission Line Model (HR-TLM). HR-TLM has the similar infrastructure with Refined TLM (RTLM) or Refined-Ladder TLM(R-LTLM), but is optimized for calibration methods. Its advantage lies in maintaining low h̊o̊_c extraction accuracy while significantly reducing the impact of structural process errors. According to the error analysis model, we verify that the extraction accuracy of HR-TLM based on R-LTLM can reach 10-9 Ωcm2 at micron scale lithography precision.

With the great advancement of semiconductor processes, the CMOS integration on both sides of wafer provides brand new scope for advanced logic technologies by fully utilizing the wafer backside, emerging as one of the key knobs to further extend the Moore’s law. Benefited from it, lateral transport transistors can be stacked in a back-to-back fashion to form the Flip FET (FFET), doubling the transistor density. Furthermore, similar concepts can be applied to vertical transistors to realize the dual-sided vertical FET (DSVFET), with better device symmetry and area efficiency. In this work, we systematically reviewed the applications of dual-sided integration for advanced logic devices, from the lateral transistors to the vertical ones. Specifically, to meet the urgent requirement of high energy efficiency computing (EEC) for future AI applications, the DSVFET was thoroughly investigated in terms of process development, electrical characteristics, circuit design and chip-level evaluation. Thanks to the adjustable vertical structure, DSVFET holds great features of both reduced parasitic and area. Area scalability of DSVFET is also confirmed at standard cell (~30%) and block (~40%) level. The block level evaluation validates the energy efficiency benefit of DSVFET at nominal Vdd range of EEC by ~15% energy delay product gain. This work validates the great potential of dual-sided integration in the next-generation logic technology.

As integrated circuits advance toward dual-side wafer-level integration, thermal budget constrained contact process has emerged as a critical bottleneck for post back-end-of-line (BEOL) integration. This work introduces a thermally sustainable contact technology utilizing self-limited Ti silicide formed at 350 degrees C, representing the lowest thermal budget ever reported for Ti silicide-based contact. By employing a revised ladder-based transmission line method, we extracted the ultra-low contact resistivities of 1.63x10(- 9)Omega.cm(2) and 4.23x10(- 9)Omega.cm(2) for n- and p-type source/drain at 350 degrees C, respectively. Benefiting from the self-limiting reaction mechanism, this approach enables precise silicidation control under ultra-low thermal budget, demonstrating full compatibility with backside thermal stability requirements ( <400 degrees C). This development may facilitate the backside device and interconnect integration while preserving the integrity of front-side processes, making a key step toward the dual-side 3D integration.

High-purity single-crystal wide-bandgap semiconductor cubic silicon carbide (3C–SiC) has the second-highest thermal conductivity among wafer-scale crystals (after diamond), making it ideal for thermal management in electronic devices. However, doping—essential for electrical property tuning—may significantly affect its thermal conductivity. While numerous theoretical studies exist, experimental data remain limited. In this work, the thermal conductivity of heavily nitrogen-doped 3C–SiC single crystals grown via the top-seeded solution growth method is measured by time-domain thermoreflectance. The results show a significant reduction (up to 30%) in thermal conductivity at nitrogen doping concentrations around 2 × 1020 cm−3. The doping concentration and distribution are investigated using secondary ion mass spectroscopy and atom probe tomography, revealing an atomic-scale uniform nitrogen distribution. Experimental results show a lower thermal conductivity reduction than previous density functional theory predictions, indicating weaker phonon–electron scattering than expected. Large-area thermal conductivity measurement and mapping reveal spatially uniform thermal conductivity in 3C–SiC at the micro-to-macroscale, emphasizing its practical utility and general high quality. These findings shed light on understanding the doping effects on thermal transport in semiconductors and support further exploration of 3C–SiC for electronics thermal management.

With the continuous downscaling of transistors, stacked transistors are considered as the most important candidate for next-generation technology due to their area-efficient nature of 3-D stacking of n/p field effect transistor (FET) at the same footprint. Previously, we reported the Flip FET (FFET) as a new approach on stacking, with unique back-to-back stacking and much more manufacturing-friendly processes compared to the monolithic complementary field effect transistor (CFET) (Mono. CFET). In this work, we further explore the potentials and challenges of the FFET in the aspects of process developments, such as fin etch, wafer bonding and flipping, substrate thinning, active fin profile optimization, thermal budgets, and metal contaminations. The FFET architecture was further extended to nanosheets. Moreover, for the thermal budget and contamination concerns, novel Multi-flipping processes (Double Flips and Triple Flips) were proposed and investigated. By carefully choosing metals/dielectrics options, the Double Flips processes show the best balancing among processes complexity, cost, and power performance (PP). Moreover, detailed comparisons on high aspect ratio (HAR) processes and PP between the FFET and the Mono. complementary field effect transistor (CFET) were conducted, proving greatly relaxed process complexity and electrical advantage in the FFET.