Checking the power grid must begin early in the design. One way of doing this is using vectorless verification which, unlike standard simulation, only requires limited information about the currents drawn from the grid, in the form of DC local and global upper-bounds, or current constraints. We extend the standard vectorless verification to allow transient constraints, where circuit currents may be bounded by different values at different times. This is useful to check the validity of candidate sequences of chip operations, each having different current requirements. We show that this framework leads to a less pessimistic estimation of voltage drops.

Checking the power distribution network of an integrated circuit must start early in the design process, when changes to the grid can be more easily implemented. Vectorless verification is a technique that achieves this goal by demanding limited information about the currents drawn from the grid. State of the art techniques that deal with RLC grids become prohibitive even for medium size grids. In...

To guarantee its safety, the power delivery network (PDN) must undergo a sequence of verification steps throughout the integrated circuit (IC) design flow. This involves checking that the voltage fluctuations in the grid remain within some user-specified safety threshold. Typically, this is done by performing a transient simulation of the grid under certain input current traces. Existing simulation tools require solving a large number of linear systems, making the tools slow for modern power grids containing billions of nodes. We propose a new simulation based approach for RC power grid verification that generates envelope upper bound waveforms on the true voltage drop waveforms. The envelope waveforms capture the peaks of the voltage drops quite accurately while requiring a much smaller number of system solves than traditional tools.

The power distribution network (PDN) of an integrated circuit (IC) must undergo various checks throughout the design flow, in order to guarantee that the voltage fluctuations are within certain user-specified safety thresholds. Vectorless verification of the PDN is one approach for verification that requires little information about the on-die logic. This verification problem has been studied extensively over the past few years and has been generally solved by first discretizing time using a particular user-defined time-step. We investigate the effect of this time-step on the quality of the solutions produced (both exact and estimates). We also propose an efficient method to specify the time-step in a way to minimize the errors introduced by the voltage drop estimates.

Electromigration (EM) in on-die metal lines is becoming a significant problem in modern integrated circuits technology. Due to the high levels of current density on the die, the large number of metal lines, and the inherent conservatism in classical full-chip EM models, designers are finding it very hard to meet the area and design specs while guaranteeing EM reliability. The EM problem is most significant in power grid lines, because unlike signal and clock lines, they do not benefit from healing due to their mostly unidirectional currents. In this paper, we develop a new model, referred to as the mesh model, for power grid EM checking which takes into account the inherent redundancy of its mesh structure while determining the reliability. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. In order to overcome the conservative assumptions that designers usually make about chip workloads, we also propose a novel vectorless mesh model technique to estimate the average minimum time-to-failure of a power grid under workload uncertainties. The results indicate that the series model, which is currently used in the industry, gives a pessimistic estimate of power grid MTF and reliability by a factor of 3-4. Finally, we exploit multithreading and grid locality to speedup our implementation by almost $6{\times }$ .

The problem of writing a specification which accurately reflects the intent of the developer has long been recognized as fundamental. We propose a method and a supporting tool to write and check a specification and an implementation using a set of use cases, \ie input-output pairs that the developer supplies. These are instances of both good (correct) and bad (incorrect) behavior. We assume that the use cases are accurate, as it is easier to generate use cases than to write an accurate specification. We incrementally construct a specification (precondition and postcondition) based on semantic feedback generated from these use cases. We check the accuracy of the constructed specification using two proposed algorithms. The first algorithm checks the accuracy of the specification against an automatically generated specification from a supplied finite domain of use cases. The second checks the accuracy of the specification via reducing its domain to a finite yet equally satisfiable domain if possible. When the specification is mature, we start to also construct a program that satisfies the specification. However, our method makes provision for the continued modification of the specification, if needed. We illustrate our method with two examples; linear search and text justify.

Electromigration (EM) in the on-die metal lines has re-emerged as a significant concern in modern VLSI circuits. The higher levels of temperature on die and the very large number of metal lines, coupled with the conservatism inherent in traditional EM checking strategies, have led to a situation where trying to guarantee EM reliability often leads to unacceptably conservative designs that may not meet the area or performance specs. Due to unidirectional currents, this problem is most significant in the power and ground grids. Thus, this work is aimed at reducing the pessimism in EM prediction for power/ground grids. There are two sources for the high pessimism: 1) the use of the traditional series model for EM checking and 2) pessimistic assumptions about the chip workload and the corresponding supply currents. To address this problem, we propose a framework for EM checking that allows users to specify conditions-of-use type constraints that help capture realistic chip workload and which includes the use of a novel mesh model for EM prediction in the grid, instead of the traditional series model.

Electromigration (EM) is re-emerging as a significant problem in modern integrated circuits (IC). Especially in power grids, due to shrinking wire widths and increasing current densities, there is little or no margin left between the predicted EM stress and that allowed by the EM design rules. Statistical Electromigration Budgeting (SEB) estimates the reliability of the grid by considering it entirely as a series system. However, a power grid with its many parallel paths has much inherent redundancy. In this paper, we propose a new model to estimate the MTF and reliability of the power grid under the influence of EM, which accounts for these redundancies. We refer to this as the mesh model. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. The proposed algorithm is quite fast and has an overall observed empirical complexity of 0(n1.4). The results indicate that the series model, which is currently used in the industry, gives a pessimistic estimate of power grid MTF and reliability by a factor of 3-4.

We present a technique and related system implementation for minimizing energy consumption in ripple carry adder blocks, and we show simulation results for the various system blocks. The method includes a tracking loop which measures the energy consumed by the load and controls, through a DC-DC converter, the supply voltage of the load. The energy consumption of the adder is calculated for a range of inputs in order to verify the efficiency of the tracking loop. Results corresponding to an 8-bit ripple carry adder show that energy savings of the order of 50%-100% are expected to be obtained when all the blocks of the circuit are running together. The system is simulated using HSPICE and Verilog-A.

In this paper, we investigate various testing techniques for detecting resistive-open defects in 16 nm CMOS technology taking into consideration the wide process variations associated with such a technology. We will use two techniques: the first is the i DDT method that detects unexpected transient power supply and ground currents by looking at their peak values or by finding the RMS value of their wavelet transform. The second method consists of measuring the propagation delay from the primary inputs to the circuit outputs. The simulation parameters that we use for the transistor models are taken from Predictive Technology Model (PTM) and the process variation of each parameter is obtained from the existing literature. Results show that the peak i DDT and wavelet techniques provide an acceptable detection percentage, while the delay test proves to be very effective in detecting resistive-open defects even in the case of extreme process variations.

In this paper, we investigate the effectiveness of different testing techniques in detecting resistive-open defects for adder circuits implemented using current and future CMOS technologies down to 22nm. We take into consideration the wide process variations associated with such technologies. The first method is based on monitoring various characteristics of the transient power supply and ground currents (i DDT ) while the second method relies on measuring the propagation delay from the primary inputs to primary outputs. The transistor models are acquired from the Predictive Technology Model website (PTM) and the percentage variations for technology parameters are obtained from the existing literature. Results show the effectiveness of the i DDT methods for small circuits. However, the capability of the method declines for larger circuits. The delay test proves to be very effective in all cases.