Side-channel attacks (SCAs), such as differential power analysis or differential electromagnetic analysis, pose a serious threat to the security of embedded systems. In the literature, few articles address the problem of securing general purpose processors (GPPs) with resourceful countermeasures. However, in many low-cost applications, where security is not critical, cryptographic algorithms are typically implemented in software. Since it has been proved that GPPs are vulnerable to SCAs, it is desirable to develop efficient mechanisms to ensure a certain level of security. In this paper, we extend side-channel countermeasures to the register transfer level description. The challenge is to create a new class of processor that executes embedded software applications, which are intrinsically protected against SCAs. For that purpose, we first investigate how to integrate into the datapath two countermeasures based on masking and hiding approaches. Through an FPGA-based processor, we then evaluate the overhead and the effectiveness of the proposed solutions against time-domain first-order attacks. We finally show that a suitable combination of countermeasures significantly increases the side-channel resistance in a cost-effective way.

An ElectroMagnetic analysis (EMA) technique is applied to Flash-based FPGA (Field Programmable Gate Arrays) ProASIC3E to measure the delay variability. Measurements show that delay variations can reach 40% according to the mapping, placement and routing used in the FPGA array, while the synthesis tool analysis show differences lower than 7%. Comparisons between the use of EMA technique in Flash and SRAM-based FPGAs are presented. The Flash-based FPGA configurable blocks and routing structures are modeled at the electrical level. Then, SPICE simulations are performed to compare the predictive variability to the measurements ones. Results obtained with EMA can support designers on selecting different parts of the FPGA array, such as distinct mapping, placements and routing wires according to application and provide a valuable feedback for the FPGA's manufacture company.

Nowadays, digital systems are becoming the main information support. This evolution implies a growing interest for the domain of cryptology regarding the conception of these systems. The hardware/software implementation has become one of the main weaknesses of security applications and hardware or side channel attacks, such as DPA (Differential Power Analysis) and CPA (Current Power Analysis), have become standard. They are now identified as the most dangerous i.e. they allow ciphering algorithm keys discovery, like those used in smartcards, with minor cost and effort. In this context, the missions of this platform, supported by the Region Languedoc Roussillon and the Universite Montpellier 2, are to analyze the security potentialities of hardware platforms and embedded systems. This platform involves disciplinary competencies like Mathematics (I3M laboratory, Montpellier), Informatics and Microelectronics (LIRMM laboratory, Montpellier) and Electronics (IES laboratory, Montpellier). Our equipment allows us to perform process characterization as well. This platform is clearly part of a scientific and technical transverse approach in the Universite Montpellier 2 and Pole MIPS (Mathematics, Informatics, Physics and System) scene.