Multilayer Ceramic Capacitors (MLCCs) are of paramount importance in electronics and ferroelectric Class II dielectrics enable outstanding energy-density values. However, the non-linear dielectric constant and associated low-frequency large-signal excitation losses of Class II MLCCs may cause critical overheating. A peak-charge based Steinmetz loss model entitled iGSE-CQ is known in literature and allows to accurately calculate MLCC low-frequency large-signal excitation losses under various operating conditions including biased and non-sinusoidal excitation voltage waveforms. Such a macroscopic iGSE-CQ model, however, is inherently limited to a specific MLCC, and in contrast to Steinmetz loss modeling for ferromagnetic inductor cores, the losses of other devices employing the same dielectric material cannot be predicted. Recent literature therefore proposed a microscopic and/or material specific MLCC Steinmetz Model entitled iGSE-CD which allows to calculate the losses of any MLCC of the same dielectric material based upon just a single set of Steinmetz parameters. However, due to the lack of information on the internal device geometry, the iGSE-CD could be verified only indirectly so far by means of a loss normalization based on the device capacitance and rated voltage. In this paper, we demonstrate the feasibility of a microscopic iGSE-CD MLCC loss model enabled by manufacturer data on the internal capacitor structure. The iGSE-CD is verified for two different MLCC series employing a conventional X7R dielectric and a novel Hiteca (with reduced non-linearity) Class II dielectric material with loss estimation error below $22\%$. This error results due to component tolerances and is acceptable, especially when compared to the loss calculation based on the datasheet information which can be off by up to a factor of ten. The analysis of the Hiteca dielectric reveals a frequency behavior different to the X7R material, and is discussed in the Appendix of this paper.

A dual three-phase active bridge (D3AB) power factor correction (PFC) rectifier features two dc ports, i.e., one on the primary side, which is not isolated from the mains, and the second, which is galvanically isolated dc port on the secondary side. A model for calculating the conducted electromagnetic interference (EMI) noise of a 7.5-kW D3AB PFC rectifier operating from a 400 V$_\mathrm{rms}$ line-to-line mains and generating dc output voltages of $V_{\mathrm{dc,1}} =$ 800 V and $V_{\mathrm{dc,2}} =$ 400 V is presented in this article. The EMI model takes into account the implications of the power levels provided at the primary- and secondary-side dc ports, i.e., $P_{1}$ and $P_{2}$, respectively, on the conducted EMI noise and is used to design an EMI filter for a hardware prototype of the D3AB converter topology, which is volume-optimized for the considered specifications. The designed filter has a volume of $0.17\,\text{dm}^{3} = 10.\text{4}\;\text{ in}^{3}$ ($0.09\text{ dm}^{3} = 5.5\text{ in}^{3}$ for the differential mode filter and $0.08\text{ dm}^{3} = 4.9\text{ in}^{3}$ for the common mode filter part). As part of the experimental verification of the model, the conducted EMI noise of the hardware prototype is measured under two different workload scenarios, i.e., $P_{1} = \text{4}\;\text{ kW}$, $P_{2} = \text{2.5}\;\text{ kW}$ and $P_{1} = 0$, $P_{2} = 6.5\text{ kW}$. Measurements show that the level of conducted EMI noise increases with increasing load on the secondary side, which is consistent with the predictions of the noise model. The complete hardware prototype achieves sinusoidal mains currents with a power factor of $\lambda = 0.994$ and a total harmonic distortion of currents lower than $5.6\%$ at the considered loads and complies with the CISPR 11 class A quasi-peak conducted EMI limit.

A recently introduced Dual Three-Phase Active Bridge Converter (D3ABC) provides two three-phase ac ports (ac ${}_{1}$ and ac ${}_{2}$ ), two dc ports (dc ${}_{1}$ and dc ${}_{2}$ ), and galvanic isolation between the ports ac ${}_{1}$ , dc ${}_{1}$ (primary side) and ac ${}_{2}$ , dc ${}_{2}$ (secondary side). Previously documented studies confirm that the D3ABC is generally capable of transferring power between all four ports. However, it has been found challenging to operate the converter if ac voltages with different line frequencies, $f_{1} \ne f_{2}$ , are present at the ports ac ${}_{1}$ and ac ${}_{2}$ . Such operation causes Low-Frequency (LF) power pulsations in the converter's dc links, leading to fluctuating dc link voltages and distorted phase currents. In this paper, a new duty-cycle dependent phase shift modulation scheme is proposed that eliminates such LF power pulsations and substantially increases the theoretical maximum transmittable power between primary and secondary sides compared to previous work. The new modulation scheme is developed on the basis of analytical considerations, which are supported by the results of numerical calculations, and verified by means of circuit simulations and experimental results. A hardware demonstrator originally designed for a rated power of $\text{8}\,$ kW when operated from ac ${}_{1}$ to dc ${}_{2}$ at the European low-voltage ac mains ( $V_{\mathrm{ac,1}} = \text{230}\,{\rm V}$ line-to-neutral rms, $V_{\mathrm{dc,1}} = \text{800}\,{\rm V}$ , $V_{\mathrm{dc,2}} = \text{400}\,{\rm V}$ ) is used for experimental verification. Since the operation with $f_{1} \ne f_{2}$ leads to an increase of the currents in the converter, the experimental verification is conducted at half voltages and for a reduced power of $\text{2}\,$ kW that is transferred from ac ${}_{1}$ to ac ${}_{2}$ at substantially different primary-side and secondary-side line frequencies of $f_{1} = \text{50}\,$ Hz and $f_{2} = \text{77}\,$ Hz. The measured results agree well with the simulated results. In particular, the dc link voltages show almost constant waveforms, which confirms the correct operation of the proposed modulation scheme.

This paper investigates the operation of the Dual Three-Phase Active Bridge (D3AB) converter topology as a multi-port converter, by taking the three-phase ac port and dc port on the primary side (ac1 and dc1) and the galvanically isolated three-phase ac port and dc port on the secondary side (ac2 and dc2) simultaneously into account. The basic working principle of the D3AB topology under multi-port operation and a strategy to achieve independent power transfer between the four ports are described. It is found that the realization of a power transfer between ac1 and ac2, which can be operated with different line voltages and line frequencies, is particularly challenging, as compared to dc1–dc2 operation. Therefore, this mode of operation is further analyzed and suitable modulation schemes are developed to achieve sinusoidal ac currents, constant dc-link voltages, and reduced low-frequency power pulsations between the ac ports. The derived analytical results are verified by means of circuit simulations and experiments, for a primary-side ac rms phase voltage of 115 V and line frequency of 50 Hz, a secondary-side ac rms phase voltage of 57.5 V and line frequency of 77 Hz, and an output power of 675 W.

Ferroelectric Class II ceramic capacitors allow for highly compact converter realizations, but are showing relatively high losses for large-signal excitations which must be taken into account in the system dimensioning. Recent literature introduced the iGSE-C Q , a Steinmetz model based on the macroscopic capacitor Q-U hysteresis, allowing to accurately predict the losses of X7R capacitors. However, the model is specific for each single device, i.e., is insufficient to characterize losses in devices of the same series and manufacturer, which are employing the same dielectric material but with different voltage rating or nominal capacitance value. In this publication, based on basic physical properties we propose a new Steinmetz model, the iGSE-C X based on the relative dielectric material D-E hysteresis, which is applicable to all devices of a capacitor series. The iGSE-C X loss modeling technique is demonstrated for the TDK X7R, the TDK X7T, as well as the Knowles Syfer X7R series. Finally, the iGSE-C X is employed to estimate the large-signal losses of the capacitors of a three-phase inverter and shown to offer sufficient accuracy for a first power circuit design.

Due to the large relative permittivity of Class II dielectrics, ceramic capacitors (CCs) from these materials promise significant volume and weight reductions in inverter and rectifier sine-wave filters, and are especially attractive in mobile applications that demand ultrahigh power density. While previous literature found large low-frequency losses in these components, no extensible loss model was proposed to accurately characterize these ferroelectric losses. In this article, we take advantage of prior art on ferromagnetic components in power electronics to propose a Steinmetz parameter-based loss modeling approach for X7R CCs, named the Improved Generalized Steinmetz Equation for CCs, or iGSE-C. This model is verified using the Sawyer-Tower circuit to measure losses in a commercially available X7R capacitor across excitation magnitude, dc bias, temperature, excitation frequency, and harmonic injection. Losses are shown to scale according to a power law with charge, with the resulting Steinmetz coefficients valid across dc bias and slightly varying as the temperature is increased. The iGSE-C accurately predicts losses for typical nonsinusoidal phase voltage waveforms with an error under 8%. Finally, the loss modeling technique is demonstrated for the sine-wave output filter of a bridge-leg arrangement with both low- and high-frequency excitations, with total capacitor losses predicted within 12% accuracy.

Compact, light-weight, efficient and reliable power converters are fundamental for the future of More Electrical Aircraft (MEA). Core elements supporting the electrification of the aerospace industry are power modules (PMs) employing exclusively SiC MOSFETs. In order to fully exploit the high switching speeds enabled by SiC, and to address the challenges arising from the parallelization of power devices, novel PM concepts must be investigated. In this paper, highly symmetrical layouts, low inductance planar interconnection technologies, and integrated buffer capacitors are explored to realize a high efficiency, fast-switching, and reliable full-SiC PM for MEA applications. A comprehensive assessment of a number of performance metrics against state-of-the-art full-SiC PMs demonstrates the benefits of the proposed design approach and manufacturing technologies. Moreover, by integrating temperature and current sensors, intelligent functions, which are crucial for the safe application of power electronics in MEA, are added to the developed PM. In this context, the use of MOSFETs’ Temperature Sensitive Electrical Parameters for online junction temperature estimation is demonstrated, allowing for non-invasive, i.e. without the need for dedicated sensors, thermal monitoring. Additionally, a highly compact gate driver, reducing the overall system volume and complexity, is designed and integrated in the housing of the PM. Finally, switching waveforms are measured during operation of the PM at 500V and 200A, proving the performance improvement enabled by the low inductance layout, the integrated snubber, and the gate driver.

The unprecedented performance potential of gallium nitride-on-silicon (GaN-on-Si) high electron mobility transistors (HEMTs) is seen as the key enabler for the design of power converters featuring extreme power density figures, as demanded in next-generation power electronics applications. However, unexpected loss mechanisms, i.e. dynamic R-d(s,on) phenomena and C-oss-losses, are appearing in currently available GaN transistors and are compromising their operation. In this paper, measurements of C-oss-losses are performed in a dedicated calorimetric measurement setup and, through a systematic approach, the root cause of the loss mechanism is potentially identified. Afterward, with the essential support of a manufacturer of power semiconductors, a novel transistor, featuring an enhanced multilayer III-N buffer, is developed according to the acquired knowledge. A significant reduction in terms of C-oss-lasses, i.e. of soft-switching losses, and the absence of dynamic R-ds,R-on phenomena are verified experimentally on the new device. These achievements enable a significant performance improvement for future soft-switching power converters featuring GaN-on-Si HEMTs.

The recently presented Dual Three-Phase Active Bridge (D3AB) converter integrates a three-phase Power Factor Corrected (PFC) rectifier and a DC-DC converter stage with galvanic isolation, originating from the Dual Active Bridge converter, in a single converter unit, and accordingly features low complexity, high efficiency, and high power density. This paper proposes a multi-objective optimization procedure that considers the objectives of low RMS transformer currents and/or switching losses in order to identify Pareto-optimal low-loss modulation schemes for the D3AB rectifier that meet given specifications, prevent power pulsation, and facilitate interleaved operation. From the obtained results, which are verified by means of detailed circuit simulations, an improved modulation scheme is selected, which, compared to conventional modulation, reduces the primary-side switching losses by 54% and the total converter losses by 11%. Due to the general nature of the presented method, the application to other three-phase rectifier/inverter topologies is directly feasible.