A 28nm SoC solution with integrated proactive power management for droop mitigation is demonstrated combining a neural droop management unit, integrated high speed power converter, and an online learning engine to combat the PDN and workload variations. The 28nm test chip integrated with CPU and accelerators achieves 59% worst-case droop reduction, 48x throttling reduction, and > 91% regulator peak efficiency, reducing performance degradation from prior fixed-model or throttling-only schemes.

We present an all-digital voltage droop monitor (VDM) with coupled ring-oscillators (CoRO) for accurate in-situ droop monitoring every clock cycle. Measurements from a 3.2mm 2 testchip in Intel 4 CMOS containing 9 3-way CoRO and baseline RO VDMs demonstrate 3X improvement in CoRO resolution $(\sim 2.6$ mV/b) over the baseline. In addition, measurements show $3 \sigma$ uncertainty (repeatability) error of CoRO VDM (+/-9mV) is $\sim25$ % lower than the baseline. The overall droop detection error improvements achieved by CoRO VDM are 12mV, 15mV and 17mV, respectively, depending on the type of calibration used - per instance/temperature/die, per temperature/die, or per die. This corresponds to associated IP power savings of 2.9%, 3.2% and 3.7% during functional use.

Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as $0.3\times $ VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates.

Over the last 25 years, the use of caches has advanced significantly in mainstream microprocessors to address the memory wall challenge. As we transformed microprocessors from single-core to multicore to manycore, innovations in the architecture, design, and management of on-die cache hierarchy were critical to enabling scaling in performance and efficiency. In addition, at the system level, as input/output (I/O) devices (e.g., networking) and accelerators (domain-specific) started to interact with general-purpose cores across shared memory, advancements in caching became important as a way of minimizing data movement and enabling faster communication. In this article, we cover some of the major advancements in cache research and development that have improved the performance and efficiency of microprocessor servers over the last 25 years. We will reflect upon several techniques including shared and distributed last-level caches (including data placement and coherence), cache Quality of Service (addressing interference between workloads), direct cache access (placing I/O data directly into CPU caches), and extending caching to off-die accelerators (CXL.cache). We will also outline potential future directions for cache research and development over the next 25 years.

A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (VRETENTION) is presented. All-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33%/28% for core/IP, with 120ns wake up latency while addressing impact of PVT variations.

A 20KB 6T-SRAM array in 10nm CMOS demonstrates 2X higher read bandwidth in burst mode operation. The doubling of bandwidth is achieved with 51% higher energy efficiency than frequency doubling and 30% better area efficiency than doubling the number of banks.

Distributed charge injection (CI) scheme featuring distributed $V_{\mathrm {MAX}}$ -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to $V_{\mathrm {CC}}$ for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of ~11% over a guard-banded baseline.

Integrated LDOs cost-effectively enable fine-grain voltage regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regulation improving both local IR-drop and transient droop response across the IP domain [1]-[3]. However, previous distributed LDOs used custom communication between a global controller and local distributed LDO controllers [1], custom communication between neighboring LDO controllers [2], and/or analog voltage sensors with associated shared VREF generation and routing [1]-[3]. This paper presents a fully synthesizable, Distributed, and scalable all-Digital LDO (D-DLDO) voltage regulator (Fig. 25.1.1) with the following salient features: (1) fast single-cycle voltage monitoring using a Digital Supply-Voltage Sensor (DSVS), (2) fast digital PID-based controller, and (3) APR-friendly and tile-able design without the need to generate or route any global or inter-LDO digital/analog signals. A test-chip is implemented with 9 DLDO units in 10nm CMOS (Fig. 25.1.7). Each DLDO unit, including its power gates (PGs), DSVS, and controller, was fully synthesized using standard library cells and industry-standard automatic placement-and-routing (APR) tools.

Distributed charge injection (CI) scheme featuring distributed VMAX-complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to VCC for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of similar to 11% over a guard-banded baseline.

A 1.09Mb, high density (HD), 1R1W 8T-bitcell SRAM is demonstrated in 10nm FinFET CMOS featuring Low Swing (LS) and Column Multiplexed (CM) bitline (BL) techniques. Read-Vmin and noise-tolerance is improved using a series NMOS clipper and a split input NAND for early keeper turnoff. Measurements show 30(40)mV lower read-Vmin, 18(30)% lower BL power for the proposed LS(LS+CM) BL schemes, with improved noise tolerance, and minimal area overhead.

An Event-driven visual data Processing Unit (EPU) exploits temporal redundancy in stationary camera video streams to localize motion-based Regions-of-Interest (RoI), saving compute FLOPs and memory bandwidth (BW) for Deep Learning (DL) based object detection. The proposed EPU supports FHD frames at 70fps and can be time-multiplexed across multiple video streams. The EPU pipeline consists of event detection, event clustering, event cluster dilation and RoI extraction and occupies 0.34mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 10nm CMOS. Frame-based, inter- and intra-frame event-driven power management schemes minimize normalized energy/pixel to 0.05pJ at 0.65V. RoI filtering with an EPU frontend improves the end-to-end (E2E) energy-efficiency of a deep-learning (DL) based vision pipeline by 5X, while improving its throughput by 4.3X.

Distributed charge injection (CI) scheme featuring distributed $V_{\mathrm {MAX}}$ -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to $V_{\mathrm {CC}}$ for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of ~11% over a guard-banded baseline.

Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and V-MIN optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.

We report a detailed analysis of neutron-induced multibit-upset (MBU) clusters measured from flip-flop arrays implemented in a 14-nm trigate CMOS. Depending on the strike location, charge collection efficiency, and circuit topology, the MBU clusters are characterized in terms of size and span, and a qualitative first-order analysis has been presented. A novel MBU analysis framework has been demonstrated that uses a weighted sliding window to characterize MBU clusters efficiently and accurately with minimal double-counting or mischaracterization of cluster size. To further explain the relative MBU cross sections, the unique MBU patterns extracted from measured data have been studied and analyzed to find layout dependencies. The results show the strong correlation between the internode proximity and MBUs. The analysis shows a higher soft error rate (SER) cross section for smaller MBU cluster size and smaller span while the bigger clusters have lower contribution toward overall MBU SER.

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.

Distributed charge injection (CI) scheme featuring distributed V MAX -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in 10-nm FinFET CMOS test-chip. A local DDD detects nearby voltage droop in two clock cycles of IP block, and quickly triggers associated CI clamps to inject charge from a high voltage rail (e.g., 1.8 V) to V CC for immediate voltage droop mitigation. Local droop controller collectively guarantees stable operation after CI is triggered, by gradually allowing the voltage regulator to take over after the droop subsides. Measured data shows droop reduction by up to 45% for a uniform transient load current transition, and by 38% in a hot-spot load current transition at 1.0 V and 2.0 GHz. The droop reduction is translated to power savings of ∼11% over a guard-banded baseline.

Graphics workloads are highly dynamic in nature, using multi-threaded SIMD execution units (EUs), fixed-function units, samplers, and media accelerators to provide ever-increasing amounts of graphics performance. These workloads are often limited by power and thermal constraints, requiring dynamic voltage/frequency scaling (DVFS) of the graphics processor (GPU). This coarse-grain DVFS, driven by a power-management IC (PMIC) setting a shared rail voltage (VIN), incurs performance loss while waiting for PLL re-lock and slow-rail voltage transitions. In addition, it does not allow a performance-critical unit (e.g. an EU) to use on demand a higher V/F (e.g. for EU turbo) without an energy penalty for the rest of the GPU.